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Wysocki" , Kyungmin Park , Sascha Hauer , Fabio Estevam , Georgi Djakov Subject: Re: [PATCH v7 5/5] arm64: dts: imx8m: Add ddr controller nodes Thread-Topic: [PATCH v7 5/5] arm64: dts: imx8m: Add ddr controller nodes Thread-Index: AQHVoX4qUUvWMnVlkEqCY7YW+VjVzQ== Date: Fri, 29 Nov 2019 05:33:55 +0000 Message-ID: References: <23e46c12c98947315229c20dea6784ad40d294c4.1574458460.git.leonard.crestez@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=leonard.crestez@nxp.com; x-originating-ip: [92.121.36.197] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 650fd6cb-af99-4959-bcfa-08d7748db9d9 x-ms-traffictypediagnostic: VI1PR04MB6221:|VI1PR04MB6221: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 0236114672 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(376002)(136003)(366004)(346002)(396003)(199004)(189003)(3846002)(6116002)(7696005)(4326008)(2906002)(8936002)(86362001)(81166006)(81156014)(8676002)(14454004)(55016002)(9686003)(4001150100001)(6436002)(6246003)(186003)(14444005)(256004)(102836004)(26005)(53546011)(6506007)(76176011)(25786009)(54906003)(110136005)(66446008)(64756008)(66556008)(66476007)(74316002)(66066001)(316002)(66946007)(7416002)(76116006)(91956017)(99286004)(446003)(305945005)(7736002)(5660300002)(44832011)(478600001)(229853002)(52536014)(71190400001)(71200400001)(33656002)(32563001);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR04MB6221;H:VI1PR04MB7023.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: +pJgowwOVjh9zjulv1XQkAYe3hfOvoV2H+EvqfI910Cnfr+RxjyRjlGtL0t9vKhqWa5INw9bx+SsC1cjUliXpPGwEUFcqDBV33XFDuGCFFkR0xViO+KMLq5GCOzSkNvt6fCfVam8qT/eDuMlrTehWzcjt9yRaLrhVnAkpGEPfLcihbnEhb86o+CNIRDzJVdvhCbyJm7X3f8igDdRMDu1OkcfQ2hThIuWJRwMruAnSlvHRjOvThwGSxCLPNWO/zUYz0XQoe9Ho0ghsultFJg0sbj+ONoJ7LBFY7qSpPSeshgQBz7JiYBF5DRxmGTvdin76+tvkpynqQXrXSYMKa7kYDxBbG9bkzKHk2pGfv4CxdUgb7tcp1HocvNT6s/HJCZfNHKLEqDqkGyzZ7IH3cpezMiHJOVLoPFcHjHW89h7nOcclJp3xiIfE2gIb+4aRfB1 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 650fd6cb-af99-4959-bcfa-08d7748db9d9 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Nov 2019 05:33:55.2056 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Eup+OmXlpjWhVoCDx0dpP9irOXPbmgO9Z40jDkqENdNMwx9WQmPagNBMMsoD7UamyhEoo/cznOv+oXbHRyszyg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6221 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 2019-11-28 4:43 PM, Adam Ford wrote:=0A= > On Fri, Nov 22, 2019 at 3:46 PM Leonard Crestez = wrote:=0A= >>=0A= >> This is used by the imx-ddrc devfreq driver to implement dynamic=0A= >> frequency scaling of DRAM.=0A= >>=0A= >> Support for proactive scaling via interconnect will come later. The=0A= >> high-performance bus masters which need that (display, vpu, gpu) are=0A= >> mostly not yet enabled in upstream anyway.=0A= >>=0A= >> Signed-off-by: Leonard Crestez =0A= >> ---=0A= >> arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 ++++++++++++++=0A= >> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 ++++++++=0A= >> .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 ++++++++++++++=0A= >> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 ++++++++=0A= >> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 +++++++++++++++++++= =0A= >> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 ++++++++=0A= >> 6 files changed, 90 insertions(+)=0A= >>=0A= >> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/b= oot/dts/freescale/imx8mm-evk.dts=0A= >> index 28ab17a277bb..ecf0d385c164 100644=0A= >> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts=0A= >> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts=0A= >> @@ -75,10 +75,28 @@=0A= >>=0A= >> &A53_0 {=0A= >> cpu-supply =3D <&buck2_reg>;=0A= >> };=0A= >>=0A= >> +&ddrc {=0A= >> + operating-points-v2 =3D <&ddrc_opp_table>;=0A= >> +=0A= >> + ddrc_opp_table: opp-table {=0A= >> + compatible =3D "operating-points-v2";=0A= >> +=0A= >> + opp-25M {=0A= >> + opp-hz =3D /bits/ 64 <25000000>;=0A= >> + };=0A= >> + opp-100M {=0A= >> + opp-hz =3D /bits/ 64 <100000000>;=0A= >> + };=0A= >> + opp-750M {=0A= >> + opp-hz =3D /bits/ 64 <750000000>;=0A= >> + };=0A= >> + };=0A= >> +};=0A= > =0A= > The SoC's device tree has the opp for the SoC. Since the SoC also has=0A= > the DDR controller, why not put the opp for the DDR into the SoC's=0A= > device tree set for its maximum rates. If the individual boards need=0A= > to change them, they can do it on a case-by-case basis.=0A= > =0A= > As more and more people add devices based on imx8m q/m/n, I can=0A= > imaging a lot of these entries will be duplicated if they base their=0A= > design on the reference evk for their respective SoC.=0A= =0A= The OPPs can vary from board to board for the same SoC. For example ddr4 = =0A= and lpddr4 variants of the NXP evk boards have different setpoints.=0A= =0A= If a default set was included in soc dtsi then some boards would end up =0A= having to use /delete-node/ and I wanted to avoid that. Last I check =0A= that feature wasn't even officially documented for dtc?=0A= =0A= Perhaps this could be revisited if it ends up being duplicated on many =0A= boards.=0A= =0A= --=0A= Regards,=0A= Leonard=0A=