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[213.179.129.39]) by smtp.gmail.com with ESMTPSA id u2-20020a1709063b8200b0098e42bef732sm5733689ejf.183.2023.07.10.01.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 01:23:55 -0700 (PDT) Date: Mon, 10 Jul 2023 10:23:53 +0200 From: Jiri Pirko To: "Kubalewski, Arkadiusz" Cc: "kuba@kernel.org" , "vadfed@meta.com" , "jonathan.lemon@gmail.com" , "pabeni@redhat.com" , "corbet@lwn.net" , "davem@davemloft.net" , "edumazet@google.com" , "vadfed@fb.com" , "Brandeburg, Jesse" , "Nguyen, Anthony L" , "M, Saeed" , "leon@kernel.org" , "richardcochran@gmail.com" , "sj@kernel.org" , "javierm@redhat.com" , "ricardo.canuelo@collabora.com" , "mst@redhat.com" , "tzimmermann@suse.de" , "Michalik, Michal" , "gregkh@linuxfoundation.org" , "jacek.lawrynowicz@linux.intel.com" , "airlied@redhat.com" , "ogabbay@kernel.org" , "arnd@arndb.de" , "nipun.gupta@amd.com" , "axboe@kernel.dk" , "linux@zary.sk" , "masahiroy@kernel.org" , "benjamin.tissoires@redhat.com" , "geert+renesas@glider.be" , "Olech, Milena" , "kuniyu@amazon.com" , "liuhangbin@gmail.com" , "hkallweit1@gmail.com" , "andy.ren@getcruise.com" , "razor@blackwall.org" , "idosch@nvidia.com" , "lucien.xin@gmail.com" , "nicolas.dichtel@6wind.com" , "phil@nwl.cc" , "claudiajkang@gmail.com" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" , "intel-wired-lan@lists.osuosl.org" , "linux-rdma@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , poros , mschmidt , "linux-clk@vger.kernel.org" , "vadim.fedorenko@linux.dev" Subject: Re: [RFC PATCH v8 08/10] ice: implement dpll interface to control cgu Message-ID: References: <20230609121853.3607724-1-arkadiusz.kubalewski@intel.com> <20230609121853.3607724-9-arkadiusz.kubalewski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Mon, Jul 03, 2023 at 02:37:18PM CEST, arkadiusz.kubalewski@intel.com wrote: >>From: Jiri Pirko >>Sent: Thursday, June 29, 2023 8:14 AM >> >>Wed, Jun 21, 2023 at 02:29:59PM CEST, jiri@resnulli.us wrote: >>>Mon, Jun 19, 2023 at 10:34:12PM CEST, arkadiusz.kubalewski@intel.com >>wrote: >>>>>From: Jiri Pirko >>>>>Sent: Saturday, June 10, 2023 6:37 PM >>>>> >>>>>Fri, Jun 09, 2023 at 02:18:51PM CEST, arkadiusz.kubalewski@intel.com >>>>>wrote: >>>>> >>>>>[...] >>>>> >>>>> >>>>>>+static int ice_dpll_mode_get(const struct dpll_device *dpll, void *priv, >>>>>>+ enum dpll_mode *mode, >>>>>>+ struct netlink_ext_ack *extack) >>>>>>+{ >>>>>>+ *mode = DPLL_MODE_AUTOMATIC; >>>>> >>>>>I don't understand how the automatic mode could work with SyncE. The >>>>>There is one pin exposed for one netdev. The SyncE daemon should select >>>>>exacly one pin. How do you achieve that? >>>>>Is is by setting DPLL_PIN_STATE_SELECTABLE on the pin-netdev you want to >>>>>select and DPLL_PIN_STATE_DISCONNECTED on the rest? >>>>> >>>>> >>>>>[...] >>>> >>>>AUTOMATIC mode autoselects highest priority valid signal. >>>>As you have pointed out, for SyncE selection, the user must be able to >>>>manually >>>>select a pin state to enable recovery of signal from particular port. >>>> >>>>In "ice" case there are 2 pins for network PHY clock signal recovery, and >>>>both >>>>are parent pins (MUX-type). There are also 4 pins assigned to netdevs >>>>(one per >>>>port). Thus passing a signal from PHY to the pin is done through the MUX- >>>>pin, >>>>by selecting proper state on pin-parent pair (where parent pins is highest >>>>prio >>>>pin on dpll). >>> >>>Could you show me some examples please? >> >>Arkadiusz, could you please reply to this? >>Thanks! >> > >Sure, sorry for the delays, let's try that. > >'ice' use case: >Enabling a PHY clock recovery for DPLL_MODE_AUTOMATIC dpll (ID#0) with PHY >recovered clock signals (PIN_ID#13) being muxed using MUX-type pin (PIN_ID#2) > >1. Set MUX-type pin to state selectable and highest priority on a dpll device >(or make sure it is already configured): >CMD_PIN_SET: > PIN_ID 2 > PIN_PARENT_DEVICE (nest) > ID 0 > PIN_STATE SELECTABLE > PIN_PRIO 0 >(assume all the other pins have prio >=1) > >2. Set connected state on a pin-parent_pin tuple where parent is a pin from #1 >CMD_PIN_SET: > PIN_ID 13 > PIN_PARENT_PIN (nest) > PIN_ID 2 > PIN_STATE CONNECTED How does this look from the perspective of a SyncE flow. Let's say you have eth0 and eth1, both is connected with a DPLL pin. Could you show how you select eth0 and then eth1? > >Thank you! >Arkadiusz > >>> >>> >>>> >>>>Thank you! >>>>Arkadiusz