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From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-tegra@vger.kernel.org>, <linux-pm@vger.kernel.org>,
	<linux-clk@vger.kernel.org>
Subject: Re: [PATCH V4 00/20] Tegra210 DFLL support
Date: Fri, 1 Feb 2019 10:49:38 +0800
Message-ID: <a2cf3ccd-658a-e004-1e66-d4f9cf1026f1@nvidia.com> (raw)
In-Reply-To: <20190128075442.GA18124@ulmo>

On 1/28/19 3:54 PM, Thierry Reding wrote:
> On Mon, Jan 28, 2019 at 09:43:00AM +0800, Joseph Lo wrote:
>> On 1/25/19 9:46 PM, Thierry Reding wrote:
>>> On Fri, Jan 04, 2019 at 11:06:42AM +0800, Joseph Lo wrote:
>>>> This series introduces support for the DFLL as a CPU clock source
>>>> on Tegra210. As Jetson TX1 uses a PWM controlled regulator IC which
>>>> is driven directly by the DFLLs PWM output, we also introduce support
>>>> for PWM regulators next to I2C controlled regulators. The DFLL output
>>>> frequency is directly controlled by the regulator voltage. The registers
>>>> for controlling the PWM are part of the DFLL IP block, so there's no
>>>> separate linux regulator object involved because the regulator IC only
>>>> supplies the rail powering the CPUs. It doesn't have any other controls.
[snip]
>>> Joseph,
>>>
>>> can you detail the dependencies between the various patches. From a
>>> brief look the CPU frequency driver changes are completely separate
>>> bits and it should be possible to apply them to the cpufreq tree.
>>>
>>> The clock changes also seem independent of the rest.
>>>
>>> Are there any dependencies at all that we need to be mindful about?
>>> Or can individual maintainers just pick up the subseries directly?
>>>
>>
>> Yes, no dependence with each other. We can apply them separately.
>> Please let me know if I need to inform cpufreq or clk maintainer to pick
>> them up.
> 
> Rafael,
> 
> the three CPU frequency patches in this series were acked by Viresh
> already, but unfortunately you don't seem to be Cc'ed on these. Are
> you okay with me picking these up into the Tegra tree and send you
> a pull request in a couple of days? That way we can get the whole
> set tested a bit in linux-next. If you'd prefer to pick these up in
> the PM tree, here are the corresponding patchwork links:
> 
> 	https://patchwork.kernel.org/patch/10747943/
> 	https://patchwork.kernel.org/patch/10747947/
> 	https://patchwork.kernel.org/patch/10747953/
> 
> I'll go and give my Acked-by on these patches if the latter is the
> way you prefer.
> 
> 
> Stephen, Mike,
> 
> the same applies for clk patches. Stephen's acked all of them and I
> think all of the series is good to go. How about if I pick up these
> up in the Tegra tree and let this all cook in linux-next for a week
> or so and then send you a pull request with these? Stephen already
> picked up a couple of fixes for clk/tegra, but I don't think any of
> those would conflict with this series.
> 
> All of that said, Joseph confirmed that there are no dependencies
> between these subsystem subseries, so if you'd prefer to pick up the
> patches into your respective trees, I have no objections to that.
> 
> Thierry
> 

Hi Rafael, Stephen,

Gental ping. Please let Thierry know if the cpufreq and DFLL clock 
related changes can go through Tegra tree.

I know Rafael did say [1] it's okay to go through Tegra tree in earlier 
comment.

Thanks,
Joseph

[1]: http://patchwork.ozlabs.org/patch/1015181/

  reply index

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-04  3:06 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2019-01-08  0:35   ` Joseph Lo
2019-01-11  8:14     ` Joseph Lo
2019-01-11 19:32   ` Rob Herring
2019-01-04  3:06 ` [PATCH V4 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2019-01-04  3:06 ` [PATCH V4 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2019-01-04  3:06 ` [PATCH V4 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2019-01-04  3:06 ` [PATCH V4 05/20] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2019-01-04  3:06 ` [PATCH V4 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2019-01-04  3:06 ` [PATCH V4 07/20] clk: tegra: dfll: support PWM regulator control Joseph Lo
2019-01-04  3:06 ` [PATCH V4 08/20] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2019-01-04  3:06 ` [PATCH V4 09/20] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2019-01-08  0:33   ` Joseph Lo
2019-01-09 18:39   ` Stephen Boyd
2019-01-04  3:06 ` [PATCH V4 11/20] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2019-01-04  3:06 ` [PATCH V4 12/20] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2019-01-04  3:06 ` [PATCH V4 14/20] arm64: dts: tegra210: add DFLL clock Joseph Lo
2019-01-04  3:06 ` [PATCH V4 15/20] arm64: dts: tegra210: add CPU clocks Joseph Lo
2019-01-04  3:06 ` [PATCH V4 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2019-01-04  3:06 ` [PATCH V4 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2019-01-04  3:07 ` [PATCH V4 18/20] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2019-01-04  3:07 ` [PATCH V4 19/20] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2019-01-04  3:07 ` [PATCH V4 20/20] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2019-01-25 13:46 ` [PATCH V4 00/20] Tegra210 DFLL support Thierry Reding
2019-01-28  1:43   ` Joseph Lo
2019-01-28  7:54     ` Thierry Reding
2019-02-01  2:49       ` Joseph Lo [this message]
2019-02-05 22:27         ` Stephen Boyd

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