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* [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
@ 2020-06-29 21:17 Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 01/13] clk: qcom: gcc: fix sm8150 GPU and NPU clocks Jonathan Marek
                   ` (10 more replies)
  0 siblings, 11 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

This series adds the missing clock drivers and dts nodes to enable
the GPU on both SM8150 and SM8250.

Note an extra patch [1] is still required for GPU to work on SM8250.

Changes in V2:
* Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the newly added
  SM8150 GPU gcc clocks
* Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL"
* Added yaml schemas to gpucc dt-bindings patches
* Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers" and changed
  gpucc patches to use it.
* Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
* Added missing rpmh regulator level for sm8250 GPU clock levels
* Use sm8150/sm8250 iommu compatibles in dts
* Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc clocks in dts

[1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca

Jonathan Marek (13):
  clk: qcom: gcc: fix sm8150 GPU and NPU clocks
  clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
  clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
  clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
  clk: qcom: gcc: remove unnecessary vco_table from SM8150
  dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings
  dt-bindings: clock: Introduce SM8250 QCOM Graphics clock bindings
  clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
  clk: qcom: Add graphics clock controller driver for SM8150
  clk: qcom: Add graphics clock controller driver for SM8250
  dt-bindings: power: Add missing rpmpd rpmh regulator level
  arm64: dts: qcom: add sm8150 GPU nodes
  arm64: dts: qcom: add sm8250 GPU nodes

 .../bindings/clock/qcom,sm8150-gpucc.yaml     |  74 +++
 .../bindings/clock/qcom,sm8250-gpucc.yaml     |  74 +++
 arch/arm64/boot/dts/qcom/sm8150.dtsi          | 136 ++++++
 arch/arm64/boot/dts/qcom/sm8250.dtsi          | 143 ++++++
 drivers/clk/qcom/Kconfig                      |  16 +
 drivers/clk/qcom/Makefile                     |   2 +
 drivers/clk/qcom/clk-alpha-pll.c              |  70 ++-
 drivers/clk/qcom/clk-alpha-pll.h              |  15 +-
 drivers/clk/qcom/gcc-sm8150.c                 |  26 +-
 drivers/clk/qcom/gdsc.c                       |  25 +
 drivers/clk/qcom/gdsc.h                       |   1 +
 drivers/clk/qcom/gpucc-sc7180.c               |  27 +-
 drivers/clk/qcom/gpucc-sdm845.c               |  27 +-
 drivers/clk/qcom/gpucc-sm8150.c               | 421 ++++++++++++++++
 drivers/clk/qcom/gpucc-sm8250.c               | 450 ++++++++++++++++++
 include/dt-bindings/clock/qcom,gpucc-sm8150.h |  40 ++
 include/dt-bindings/clock/qcom,gpucc-sm8250.h |  40 ++
 include/dt-bindings/power/qcom-rpmpd.h        |   1 +
 18 files changed, 1479 insertions(+), 109 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
 create mode 100644 drivers/clk/qcom/gpucc-sm8150.c
 create mode 100644 drivers/clk/qcom/gpucc-sm8250.c
 create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h
 create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h

-- 
2.26.1


^ permalink raw reply	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 01/13] clk: qcom: gcc: fix sm8150 GPU and NPU clocks
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 02/13] clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL Jonathan Marek
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	Vinod Koul, open list:COMMON CLK FRAMEWORK, open list

Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it
should be a 500us delay and not skip, however this matches what was done
for other clocks that had 500us delay in downstream.

Fixes: f73a4230d5bb ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/gcc-sm8150.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 72524cf11048..55e9d6d75a0c 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -1617,6 +1617,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
 };
 
 static struct clk_branch gcc_gpu_gpll0_clk_src = {
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x52004,
 		.enable_mask = BIT(15),
@@ -1632,13 +1633,14 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
 };
 
 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x52004,
 		.enable_mask = BIT(16),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_gpu_gpll0_div_clk_src",
 			.parent_hws = (const struct clk_hw *[]){
-				&gcc_gpu_gpll0_clk_src.clkr.hw },
+				&gpll0_out_even.clkr.hw },
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1729,6 +1731,7 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = {
 };
 
 static struct clk_branch gcc_npu_gpll0_clk_src = {
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x52004,
 		.enable_mask = BIT(18),
@@ -1744,13 +1747,14 @@ static struct clk_branch gcc_npu_gpll0_clk_src = {
 };
 
 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x52004,
 		.enable_mask = BIT(19),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_npu_gpll0_div_clk_src",
 			.parent_hws = (const struct clk_hw *[]){
-				&gcc_npu_gpll0_clk_src.clkr.hw },
+				&gpll0_out_even.clkr.hw },
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 02/13] clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 01/13] clk: qcom: gcc: fix sm8150 GPU and NPU clocks Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 03/13] clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid Jonathan Marek
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	Taniya Das, Deepak Katragadda, Vinod Koul,
	open list:COMMON CLK FRAMEWORK, open list

0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.

Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/clk-alpha-pll.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 9b2dfa08acb2..1325139173c9 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -56,7 +56,6 @@
 #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
 #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
 #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])
-#define PLL_CAL_VAL(p)		((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
 
 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 	[CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
@@ -115,7 +114,6 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_STATUS] = 0x30,
 		[PLL_OFF_OPMODE] = 0x38,
 		[PLL_OFF_ALPHA_VAL] = 0x40,
-		[PLL_OFF_CAL_VAL] = 0x44,
 	},
 	[CLK_ALPHA_PLL_TYPE_LUCID] =  {
 		[PLL_OFF_L_VAL] = 0x04,
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 03/13] clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 01/13] clk: qcom: gcc: fix sm8150 GPU and NPU clocks Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 02/13] clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 04/13] clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll Jonathan Marek
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

Fixed ops were already identical, this adds support for non-fixed ops by
sharing between trion and lucid.

This also changes the names for trion ops to be consistent with the rest.

Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for
lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/clk-alpha-pll.c | 58 ++++++++++----------------------
 drivers/clk/qcom/clk-alpha-pll.h | 17 ++++++----
 drivers/clk/qcom/gcc-sm8150.c    |  8 ++---
 3 files changed, 32 insertions(+), 51 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 1325139173c9..be7ffeae21b1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -101,21 +101,6 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_FRAC] = 0x38,
 	},
 	[CLK_ALPHA_PLL_TYPE_TRION] = {
-		[PLL_OFF_L_VAL] = 0x04,
-		[PLL_OFF_CAL_L_VAL] = 0x08,
-		[PLL_OFF_USER_CTL] = 0x0c,
-		[PLL_OFF_USER_CTL_U] = 0x10,
-		[PLL_OFF_USER_CTL_U1] = 0x14,
-		[PLL_OFF_CONFIG_CTL] = 0x18,
-		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
-		[PLL_OFF_CONFIG_CTL_U1] = 0x20,
-		[PLL_OFF_TEST_CTL] = 0x24,
-		[PLL_OFF_TEST_CTL_U] = 0x28,
-		[PLL_OFF_STATUS] = 0x30,
-		[PLL_OFF_OPMODE] = 0x38,
-		[PLL_OFF_ALPHA_VAL] = 0x40,
-	},
-	[CLK_ALPHA_PLL_TYPE_LUCID] =  {
 		[PLL_OFF_L_VAL] = 0x04,
 		[PLL_OFF_CAL_L_VAL] = 0x08,
 		[PLL_OFF_USER_CTL] = 0x0c,
@@ -154,9 +139,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define PLL_OUT_MASK		0x7
 #define PLL_RATE_MARGIN		500
 
-/* LUCID PLL specific settings and offsets */
-#define LUCID_PLL_CAL_VAL	0x44
-#define LUCID_PCAL_DONE		BIT(26)
+/* TRION PLL specific settings and offsets */
+#define TRION_PLL_CAL_VAL	0x44
+#define TRION_PCAL_DONE		BIT(26)
 
 #define pll_alpha_width(p)					\
 		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\
@@ -910,14 +895,14 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
 
-const struct clk_ops clk_trion_fixed_pll_ops = {
+const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
 	.enable = clk_trion_pll_enable,
 	.disable = clk_trion_pll_disable,
 	.is_enabled = clk_trion_pll_is_enabled,
 	.recalc_rate = clk_trion_pll_recalc_rate,
 	.round_rate = clk_alpha_pll_round_rate,
 };
-EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
+EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
 
 static unsigned long
 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
@@ -1337,12 +1322,12 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 				  val << PLL_POST_DIV_SHIFT);
 }
 
-const struct clk_ops clk_trion_pll_postdiv_ops = {
+const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
 	.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
 	.round_rate = clk_trion_pll_postdiv_round_rate,
 	.set_rate = clk_trion_pll_postdiv_set_rate,
 };
-EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
 
 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
 				unsigned long rate, unsigned long *prate)
@@ -1397,13 +1382,13 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
  * @regmap: register map
  * @config: configuration to apply for pll
  */
-void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			     const struct alpha_pll_config *config)
 {
 	if (config->l)
 		regmap_write(regmap, PLL_L_VAL(pll), config->l);
 
-	regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);
+	regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
 
 	if (config->alpha)
 		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
@@ -1456,13 +1441,13 @@ void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 	/* Place the PLL in STANDBY mode */
 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
 }
-EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);
+EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
 
 /*
- * The Lucid PLL requires a power-on self-calibration which happens when the
+ * The TRION PLL requires a power-on self-calibration which happens when the
  * PLL comes out of reset. Calibrate in case it is not completed.
  */
-static int alpha_pll_lucid_prepare(struct clk_hw *hw)
+static int alpha_pll_trion_prepare(struct clk_hw *hw)
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 	u32 regval;
@@ -1470,7 +1455,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
 
 	/* Return early if calibration is not needed. */
 	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
-	if (regval & LUCID_PCAL_DONE)
+	if (regval & TRION_PCAL_DONE)
 		return 0;
 
 	/* On/off to calibrate */
@@ -1481,7 +1466,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
 	return ret;
 }
 
-static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
+static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
 				    unsigned long prate)
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
@@ -1535,26 +1520,17 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
 	return 0;
 }
 
-const struct clk_ops clk_alpha_pll_lucid_ops = {
-	.prepare = alpha_pll_lucid_prepare,
+const struct clk_ops clk_alpha_pll_trion_ops = {
+	.prepare = alpha_pll_trion_prepare,
 	.enable = clk_trion_pll_enable,
 	.disable = clk_trion_pll_disable,
 	.is_enabled = clk_trion_pll_is_enabled,
 	.recalc_rate = clk_trion_pll_recalc_rate,
 	.round_rate = clk_alpha_pll_round_rate,
-	.set_rate = alpha_pll_lucid_set_rate,
+	.set_rate = alpha_pll_trion_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
 
-const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {
-	.enable = clk_trion_pll_enable,
-	.disable = clk_trion_pll_disable,
-	.is_enabled = clk_trion_pll_is_enabled,
-	.recalc_rate = clk_trion_pll_recalc_rate,
-	.round_rate = clk_alpha_pll_round_rate,
-};
-EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);
-
 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
 	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
 	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 704674a153b6..67f1fd271931 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -14,7 +14,7 @@ enum {
 	CLK_ALPHA_PLL_TYPE_BRAMMO,
 	CLK_ALPHA_PLL_TYPE_FABIA,
 	CLK_ALPHA_PLL_TYPE_TRION,
-	CLK_ALPHA_PLL_TYPE_LUCID,
+	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
 	CLK_ALPHA_PLL_TYPE_MAX,
 };
 
@@ -128,18 +128,23 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops;
 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
 
-extern const struct clk_ops clk_alpha_pll_lucid_ops;
-extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;
+extern const struct clk_ops clk_alpha_pll_trion_ops;
+extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
+
+#define clk_alpha_pll_lucid_ops clk_alpha_pll_trion_ops
+#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
 
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			     const struct alpha_pll_config *config);
 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 				const struct alpha_pll_config *config);
-void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			     const struct alpha_pll_config *config);
+#define clk_lucid_pll_configure(pll, regmap, config) \
+	clk_trion_pll_configure(pll, regmap, config)
+
 
-extern const struct clk_ops clk_trion_fixed_pll_ops;
-extern const struct clk_ops clk_trion_pll_postdiv_ops;
 
 #endif
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 55e9d6d75a0c..d7778def37da 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -53,7 +53,7 @@ static struct clk_alpha_pll gpll0 = {
 				.name = "bi_tcxo",
 			},
 			.num_parents = 1,
-			.ops = &clk_trion_fixed_pll_ops,
+			.ops = &clk_alpha_pll_fixed_trion_ops,
 		},
 	},
 };
@@ -79,7 +79,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
 			.hw = &gpll0.clkr.hw,
 		},
 		.num_parents = 1,
-		.ops = &clk_trion_pll_postdiv_ops,
+		.ops = &clk_alpha_pll_postdiv_trion_ops,
 	},
 };
 
@@ -98,7 +98,7 @@ static struct clk_alpha_pll gpll7 = {
 				.name = "bi_tcxo",
 			},
 			.num_parents = 1,
-			.ops = &clk_trion_fixed_pll_ops,
+			.ops = &clk_alpha_pll_fixed_trion_ops,
 		},
 	},
 };
@@ -118,7 +118,7 @@ static struct clk_alpha_pll gpll9 = {
 				.name = "bi_tcxo",
 			},
 			.num_parents = 1,
-			.ops = &clk_trion_fixed_pll_ops,
+			.ops = &clk_alpha_pll_fixed_trion_ops,
 		},
 	},
 };
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 04/13] clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (2 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 03/13] clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 05/13] clk: qcom: gcc: remove unnecessary vco_table from SM8150 Jonathan Marek
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

Lucid PCAL_DONE is different from trion.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/clk-alpha-pll.c | 28 ++++++++++++++++++++++++++--
 drivers/clk/qcom/clk-alpha-pll.h |  2 +-
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index be7ffeae21b1..26139ef005e4 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -143,6 +143,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define TRION_PLL_CAL_VAL	0x44
 #define TRION_PCAL_DONE		BIT(26)
 
+/* LUCID PLL specific settings and offsets */
+#define LUCID_PCAL_DONE		BIT(27)
+
 #define pll_alpha_width(p)					\
 		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\
 				 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -1447,7 +1450,7 @@ EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
  * The TRION PLL requires a power-on self-calibration which happens when the
  * PLL comes out of reset. Calibrate in case it is not completed.
  */
-static int alpha_pll_trion_prepare(struct clk_hw *hw)
+static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 	u32 regval;
@@ -1455,7 +1458,7 @@ static int alpha_pll_trion_prepare(struct clk_hw *hw)
 
 	/* Return early if calibration is not needed. */
 	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
-	if (regval & TRION_PCAL_DONE)
+	if (regval & pcal_done)
 		return 0;
 
 	/* On/off to calibrate */
@@ -1466,6 +1469,16 @@ static int alpha_pll_trion_prepare(struct clk_hw *hw)
 	return ret;
 }
 
+static int alpha_pll_trion_prepare(struct clk_hw *hw)
+{
+	return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
+}
+
+static int alpha_pll_lucid_prepare(struct clk_hw *hw)
+{
+	return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
+}
+
 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
 				    unsigned long prate)
 {
@@ -1529,6 +1542,17 @@ const struct clk_ops clk_alpha_pll_trion_ops = {
 	.round_rate = clk_alpha_pll_round_rate,
 	.set_rate = alpha_pll_trion_set_rate,
 };
+EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
+
+const struct clk_ops clk_alpha_pll_lucid_ops = {
+	.prepare = alpha_pll_lucid_prepare,
+	.enable = clk_trion_pll_enable,
+	.disable = clk_trion_pll_disable,
+	.is_enabled = clk_trion_pll_is_enabled,
+	.recalc_rate = clk_trion_pll_recalc_rate,
+	.round_rate = clk_alpha_pll_round_rate,
+	.set_rate = alpha_pll_trion_set_rate,
+};
 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
 
 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 67f1fd271931..69337c1b5850 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -132,7 +132,7 @@ extern const struct clk_ops clk_alpha_pll_trion_ops;
 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
 
-#define clk_alpha_pll_lucid_ops clk_alpha_pll_trion_ops
+extern const struct clk_ops clk_alpha_pll_lucid_ops;
 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
 
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 05/13] clk: qcom: gcc: remove unnecessary vco_table from SM8150
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (3 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 04/13] clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings Jonathan Marek
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

The fixed alpha pll ops only use it for clamping in round_rate, which is
unnecessary. This is consistent with SM8250 GCC not using vco_table.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/gcc-sm8150.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index d7778def37da..8e9b5b3cceaf 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -34,14 +34,8 @@ enum {
 	P_SLEEP_CLK,
 };
 
-static const struct pll_vco trion_vco[] = {
-	{ 249600000, 2000000000, 0 },
-};
-
 static struct clk_alpha_pll gpll0 = {
 	.offset = 0x0,
-	.vco_table = trion_vco,
-	.num_vco = ARRAY_SIZE(trion_vco),
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 	.clkr = {
 		.enable_reg = 0x52000,
@@ -85,8 +79,6 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
 
 static struct clk_alpha_pll gpll7 = {
 	.offset = 0x1a000,
-	.vco_table = trion_vco,
-	.num_vco = ARRAY_SIZE(trion_vco),
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 	.clkr = {
 		.enable_reg = 0x52000,
@@ -105,8 +97,6 @@ static struct clk_alpha_pll gpll7 = {
 
 static struct clk_alpha_pll gpll9 = {
 	.offset = 0x1c000,
-	.vco_table = trion_vco,
-	.num_vco = ARRAY_SIZE(trion_vco),
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 	.clkr = {
 		.enable_reg = 0x52000,
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (4 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 05/13] clk: qcom: gcc: remove unnecessary vco_table from SM8150 Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-07-02 20:43   ` Rob Herring
  2020-07-02 20:44   ` Rob Herring
  2020-06-29 21:17 ` [RESEND PATCH v2 07/13] dt-bindings: clock: Introduce SM8250 " Jonathan Marek
                   ` (4 subsequent siblings)
  10 siblings, 2 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	Rob Herring, open list:COMMON CLK FRAMEWORK,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list

Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8150 SoCs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 .../bindings/clock/qcom,sm8150-gpucc.yaml     | 74 +++++++++++++++++++
 include/dt-bindings/clock/qcom,gpucc-sm8150.h | 40 ++++++++++
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
new file mode 100644
index 000000000000..683b50dd3492
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8150-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding for SM8150
+
+maintainers:
+  -
+
+description: |
+  Qualcomm graphics clock control module which supports the clocks, resets and
+  power domains on SM8150.
+
+  See also dt-bindings/clock/qcom,gpucc-sm8150.h.
+
+properties:
+  compatible:
+    const: qcom,sm8150-gpucc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: GPLL0 main branch source
+      - description: GPLL0 div branch source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: gcc_gpu_gpll0_clk_src
+      - const: gcc_gpu_gpll0_div_clk_src
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@2c90000 {
+      compatible = "qcom,sm8150-gpucc";
+      reg = <0x2c90000 0x9000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+      clock-names = "bi_tcxo",
+                    "gcc_gpu_gpll0_clk_src",
+                    "gcc_gpu_gpll0_div_clk_src";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8150.h b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
new file mode 100644
index 000000000000..e7cac7fe9739
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK				0
+#define GPU_CC_CRC_AHB_CLK			1
+#define GPU_CC_CX_APB_CLK			2
+#define GPU_CC_CX_GMU_CLK			3
+#define GPU_CC_CX_QDSS_AT_CLK			4
+#define GPU_CC_CX_QDSS_TRIG_CLK			5
+#define GPU_CC_CX_QDSS_TSCTR_CLK		6
+#define GPU_CC_CX_SNOC_DVM_CLK			7
+#define GPU_CC_CXO_AON_CLK			8
+#define GPU_CC_CXO_CLK				9
+#define GPU_CC_GMU_CLK_SRC			10
+#define GPU_CC_GX_GMU_CLK			11
+#define GPU_CC_GX_QDSS_TSCTR_CLK		12
+#define GPU_CC_GX_VSENSE_CLK			13
+#define GPU_CC_PLL1				14
+#define GPU_CC_PLL_TEST_CLK			15
+#define GPU_CC_SLEEP_CLK			16
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_CX_BCR			0
+#define GPUCC_GPU_CC_GFX3D_AON_BCR		1
+#define GPUCC_GPU_CC_GMU_BCR			2
+#define GPUCC_GPU_CC_GX_BCR			3
+#define GPUCC_GPU_CC_SPDM_BCR			4
+#define GPUCC_GPU_CC_XO_BCR			5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC				0
+#define GPU_GX_GDSC				1
+
+#endif
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 07/13] dt-bindings: clock: Introduce SM8250 QCOM Graphics clock bindings
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (5 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-07-02 20:46   ` Rob Herring
  2020-06-29 21:17 ` [RESEND PATCH v2 08/13] clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers Jonathan Marek
                   ` (3 subsequent siblings)
  10 siblings, 1 reply; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	Rob Herring, open list:COMMON CLK FRAMEWORK,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list

Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8250 SoCs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 .../bindings/clock/qcom,sm8250-gpucc.yaml     | 74 +++++++++++++++++++
 include/dt-bindings/clock/qcom,gpucc-sm8250.h | 40 ++++++++++
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
new file mode 100644
index 000000000000..2b9c8f97b76d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8250-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding for SM8250
+
+maintainers:
+  -
+
+description: |
+  Qualcomm graphics clock control module which supports the clocks, resets and
+  power domains on SM8250.
+
+  See also dt-bindings/clock/qcom,gpucc-sm8250.h.
+
+properties:
+  compatible:
+    const: qcom,sm8250-gpucc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: GPLL0 main branch source
+      - description: GPLL0 div branch source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: gcc_gpu_gpll0_clk_src
+      - const: gcc_gpu_gpll0_div_clk_src
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@3d90000 {
+      compatible = "qcom,sm8250-gpucc";
+      reg = <0x3d90000 0x9000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+      clock-names = "bi_tcxo",
+                    "gcc_gpu_gpll0_clk_src",
+                    "gcc_gpu_gpll0_div_clk_src";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
new file mode 100644
index 000000000000..c8fe64e399fd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK				0
+#define GPU_CC_CRC_AHB_CLK			1
+#define GPU_CC_CX_APB_CLK			2
+#define GPU_CC_CX_GMU_CLK			3
+#define GPU_CC_CX_QDSS_AT_CLK			4
+#define GPU_CC_CX_QDSS_TRIG_CLK			5
+#define GPU_CC_CX_QDSS_TSCTR_CLK		6
+#define GPU_CC_CX_SNOC_DVM_CLK			7
+#define GPU_CC_CXO_AON_CLK			8
+#define GPU_CC_CXO_CLK				9
+#define GPU_CC_GMU_CLK_SRC			10
+#define GPU_CC_GX_GMU_CLK			11
+#define GPU_CC_GX_QDSS_TSCTR_CLK		12
+#define GPU_CC_GX_VSENSE_CLK			13
+#define GPU_CC_PLL1				14
+#define GPU_CC_SLEEP_CLK			15
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		16
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_ACD_BCR			0
+#define GPUCC_GPU_CC_CX_BCR			1
+#define GPUCC_GPU_CC_GFX3D_AON_BCR		2
+#define GPUCC_GPU_CC_GMU_BCR			3
+#define GPUCC_GPU_CC_GX_BCR			4
+#define GPUCC_GPU_CC_XO_BCR			5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC				0
+#define GPU_GX_GDSC				1
+
+#endif
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 08/13] clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (6 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 07/13] dt-bindings: clock: Introduce SM8250 " Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 09/13] clk: qcom: Add graphics clock controller driver for SM8150 Jonathan Marek
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

All gpucc drivers need this, so move it to common code instead of
duplicating it in every gpucc driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/gdsc.c         | 25 +++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h         |  1 +
 drivers/clk/qcom/gpucc-sc7180.c | 27 +--------------------------
 drivers/clk/qcom/gpucc-sdm845.c | 27 +--------------------------
 4 files changed, 28 insertions(+), 52 deletions(-)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 04944f11659b..628397703717 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -433,3 +433,28 @@ void gdsc_unregister(struct gdsc_desc *desc)
 	}
 	of_genpd_del_provider(dev->of_node);
 }
+
+/*
+ * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
+ * running in the CX domain so the CPU doesn't need to know anything about the
+ * GX domain EXCEPT....
+ *
+ * Hardware constraints dictate that the GX be powered down before the CX. If
+ * the GMU crashes it could leave the GX on. In order to successfully bring back
+ * the device the CPU needs to disable the GX headswitch. There being no sane
+ * way to reach in and touch that register from deep inside the GPU driver we
+ * need to set up the infrastructure to be able to ensure that the GPU can
+ * ensure that the GX is off during this super special case. We do this by
+ * defining a GX gdsc with a dummy enable function and a "default" disable
+ * function.
+ *
+ * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
+ * driver. During power up, nothing will happen from the CPU (and the GMU will
+ * power up normally but during power down this will ensure that the GX domain
+ * is *really* off - this gives us a semi standard way of doing what we need.
+ */
+int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
+{
+	/* Do nothing but give genpd the impression that we were successful */
+	return 0;
+}
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index c36fc26dcdff..1896bfb2bbd1 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -68,6 +68,7 @@ struct gdsc_desc {
 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
 		  struct regmap *);
 void gdsc_unregister(struct gdsc_desc *desc);
+int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
 #else
 static inline int gdsc_register(struct gdsc_desc *desc,
 				struct reset_controller_dev *rcdev,
diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c
index 7b656b6aeced..88a739b6fec3 100644
--- a/drivers/clk/qcom/gpucc-sc7180.c
+++ b/drivers/clk/qcom/gpucc-sc7180.c
@@ -170,37 +170,12 @@ static struct gdsc cx_gdsc = {
 	.flags = VOTABLE,
 };
 
-/*
- * On SC7180 the GPU GX domain is *almost* entirely controlled by the GMU
- * running in the CX domain so the CPU doesn't need to know anything about the
- * GX domain EXCEPT....
- *
- * Hardware constraints dictate that the GX be powered down before the CX. If
- * the GMU crashes it could leave the GX on. In order to successfully bring back
- * the device the CPU needs to disable the GX headswitch. There being no sane
- * way to reach in and touch that register from deep inside the GPU driver we
- * need to set up the infrastructure to be able to ensure that the GPU can
- * ensure that the GX is off during this super special case. We do this by
- * defining a GX gdsc with a dummy enable function and a "default" disable
- * function.
- *
- * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
- * driver. During power up, nothing will happen from the CPU (and the GMU will
- * power up normally but during power down this will ensure that the GX domain
- * is *really* off - this gives us a semi standard way of doing what we need.
- */
-static int gx_gdsc_enable(struct generic_pm_domain *domain)
-{
-	/* Do nothing but give genpd the impression that we were successful */
-	return 0;
-}
-
 static struct gdsc gx_gdsc = {
 	.gdscr = 0x100c,
 	.clamp_io_ctrl = 0x1508,
 	.pd = {
 		.name = "gx_gdsc",
-		.power_on = gx_gdsc_enable,
+		.power_on = gdsc_gx_do_nothing_enable,
 	},
 	.pwrsts = PWRSTS_OFF_ON,
 	.flags = CLAMP_IO,
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
index e40efba1bf7d..5663698b306b 100644
--- a/drivers/clk/qcom/gpucc-sdm845.c
+++ b/drivers/clk/qcom/gpucc-sdm845.c
@@ -131,37 +131,12 @@ static struct gdsc gpu_cx_gdsc = {
 	.flags = VOTABLE,
 };
 
-/*
- * On SDM845 the GPU GX domain is *almost* entirely controlled by the GMU
- * running in the CX domain so the CPU doesn't need to know anything about the
- * GX domain EXCEPT....
- *
- * Hardware constraints dictate that the GX be powered down before the CX. If
- * the GMU crashes it could leave the GX on. In order to successfully bring back
- * the device the CPU needs to disable the GX headswitch. There being no sane
- * way to reach in and touch that register from deep inside the GPU driver we
- * need to set up the infrastructure to be able to ensure that the GPU can
- * ensure that the GX is off during this super special case. We do this by
- * defining a GX gdsc with a dummy enable function and a "default" disable
- * function.
- *
- * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
- * driver. During power up, nothing will happen from the CPU (and the GMU will
- * power up normally but during power down this will ensure that the GX domain
- * is *really* off - this gives us a semi standard way of doing what we need.
- */
-static int gx_gdsc_enable(struct generic_pm_domain *domain)
-{
-	/* Do nothing but give genpd the impression that we were successful */
-	return 0;
-}
-
 static struct gdsc gpu_gx_gdsc = {
 	.gdscr = 0x100c,
 	.clamp_io_ctrl = 0x1508,
 	.pd = {
 		.name = "gpu_gx_gdsc",
-		.power_on = gx_gdsc_enable,
+		.power_on = gdsc_gx_do_nothing_enable,
 	},
 	.pwrsts = PWRSTS_OFF_ON,
 	.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 09/13] clk: qcom: Add graphics clock controller driver for SM8150
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (7 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 08/13] clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-06-29 21:17 ` [RESEND PATCH v2 10/13] clk: qcom: Add graphics clock controller driver for SM8250 Jonathan Marek
  2020-07-03 15:03 ` [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Dmitry Baryshkov
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	open list, open list:COMMON CLK FRAMEWORK

Add support for the graphics clock controller found on SM8150
based devices. This would allow graphics drivers to probe and
control their clocks.

This is copied from the downstream kernel, adapted for upstream.
For example, GDSCs have been added.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/Kconfig        |   8 +
 drivers/clk/qcom/Makefile       |   1 +
 drivers/clk/qcom/gpucc-sm8150.c | 421 ++++++++++++++++++++++++++++++++
 3 files changed, 430 insertions(+)
 create mode 100644 drivers/clk/qcom/gpucc-sm8150.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index cde6ca90a06b..1bf5e927ee0d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -391,6 +391,14 @@ config SM_GCC_8250
 	  Say Y if you want to use peripheral devices such as UART,
 	  SPI, I2C, USB, SD/UFS, PCIe etc.
 
+config SM_GPUCC_8150
+	tristate "SM8150 Graphics Clock Controller"
+	select SM_GCC_8150
+	help
+	  Support for the graphics clock controller on SM8150 devices.
+	  Say Y if you want to support graphics controller devices and
+	  functionality such as 3D graphics.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7ec8561a1270..f819663c53a6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
+obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c
new file mode 100644
index 000000000000..dfeb8a5ad005
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-sm8150.c
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "reset.h"
+#include "gdsc.h"
+
+enum {
+	P_BI_TCXO,
+	P_CORE_BI_PLL_TEST_SE,
+	P_GPLL0_OUT_MAIN,
+	P_GPLL0_OUT_MAIN_DIV,
+	P_GPU_CC_PLL0_OUT_MAIN,
+	P_GPU_CC_PLL1_OUT_MAIN,
+};
+
+static const struct parent_map gpu_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
+	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
+	{ P_GPLL0_OUT_MAIN, 5 },
+	{ P_GPLL0_OUT_MAIN_DIV, 6 },
+	{ P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gpu_cc_parent_names_0[] = {
+	"bi_tcxo",
+	"gpu_cc_pll0",
+	"gpu_cc_pll1",
+	"gcc_gpu_gpll0_clk_src",
+	"gcc_gpu_gpll0_div_clk_src",
+	"core_bi_pll_test_se",
+};
+
+static const struct pll_vco trion_vco[] = {
+	{ 249600000, 2000000000, 0 },
+};
+
+static struct alpha_pll_config gpu_cc_pll1_config = {
+	.l = 0x1a,
+	.alpha = 0xaaa,
+	.config_ctl_val = 0x20485699,
+	.config_ctl_hi_val = 0x00002267,
+	.config_ctl_hi1_val = 0x00000024,
+	.test_ctl_val = 0x00000000,
+	.test_ctl_hi_val = 0x00000002,
+	.test_ctl_hi1_val = 0x00000000,
+	.user_ctl_val = 0x00000000,
+	.user_ctl_hi_val = 0x00000805,
+	.user_ctl_hi1_val = 0x000000d0,
+};
+
+static struct clk_alpha_pll gpu_cc_pll1 = {
+	.offset = 0x100,
+	.vco_table = trion_vco,
+	.num_vco = ARRAY_SIZE(trion_vco),
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_pll1",
+			.parent_names = (const char *[]){ "bi_tcxo" },
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_trion_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
+	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
+	.cmd_rcgr = 0x1120,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = gpu_cc_parent_map_0,
+	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gpu_cc_gmu_clk_src",
+		.parent_names = gpu_cc_parent_names_0,
+		.num_parents = 6,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gpu_cc_ahb_clk = {
+	.halt_reg = 0x1078,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x1078,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_crc_ahb_clk = {
+	.halt_reg = 0x107c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x107c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_crc_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_apb_clk = {
+	.halt_reg = 0x1088,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1088,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_apb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_gmu_clk = {
+	.halt_reg = 0x1098,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1098,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_gmu_clk",
+			.parent_names = (const char *[]){
+				"gpu_cc_gmu_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_qdss_at_clk = {
+	.halt_reg = 0x1080,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1080,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_qdss_at_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
+	.halt_reg = 0x1094,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1094,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_qdss_trig_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
+	.halt_reg = 0x1084,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1084,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_qdss_tsctr_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
+	.halt_reg = 0x108c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x108c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_snoc_dvm_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cxo_aon_clk = {
+	.halt_reg = 0x1004,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cxo_aon_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cxo_clk = {
+	.halt_reg = 0x109c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x109c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cxo_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_gx_gmu_clk = {
+	.halt_reg = 0x1064,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1064,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_gx_gmu_clk",
+			.parent_names = (const char *[]){
+				"gpu_cc_gmu_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
+	.halt_reg = 0x105c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x105c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_gx_qdss_tsctr_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_gx_vsense_clk = {
+	.halt_reg = 0x1058,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_gx_vsense_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_pll_test_clk = {
+	.halt_reg = 0x110c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x110c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_pll_test_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_sleep_clk = {
+	.halt_reg = 0x1090,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1090,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_sleep_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct gdsc gpu_cx_gdsc = {
+	.gdscr = 0x106c,
+	.gds_hw_ctrl = 0x1540,
+	.pd = {
+		.name = "gpu_cx_gdsc",
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = VOTABLE,
+};
+
+static struct gdsc gpu_gx_gdsc = {
+	.gdscr = 0x100c,
+	.clamp_io_ctrl = 0x1508,
+	.pd = {
+		.name = "gpu_gx_gdsc",
+		.power_on = gdsc_gx_do_nothing_enable,
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
+};
+
+static struct clk_regmap *gpu_cc_sm8150_clocks[] = {
+	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
+	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
+	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
+	[GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
+	[GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
+	[GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
+	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
+	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
+	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
+	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
+	[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
+	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
+	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
+	[GPU_CC_PLL_TEST_CLK] = &gpu_cc_pll_test_clk.clkr,
+	[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
+};
+
+static const struct qcom_reset_map gpu_cc_sm8150_resets[] = {
+	[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
+	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
+	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
+	[GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },
+	[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
+};
+
+static struct gdsc *gpu_cc_sm8150_gdscs[] = {
+	[GPU_CX_GDSC] = &gpu_cx_gdsc,
+	[GPU_GX_GDSC] = &gpu_gx_gdsc,
+};
+
+static const struct regmap_config gpu_cc_sm8150_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x8008,
+	.fast_io	= true,
+};
+
+static const struct qcom_cc_desc gpu_cc_sm8150_desc = {
+	.config = &gpu_cc_sm8150_regmap_config,
+	.clks = gpu_cc_sm8150_clocks,
+	.num_clks = ARRAY_SIZE(gpu_cc_sm8150_clocks),
+	.resets = gpu_cc_sm8150_resets,
+	.num_resets = ARRAY_SIZE(gpu_cc_sm8150_resets),
+	.gdscs = gpu_cc_sm8150_gdscs,
+	.num_gdscs = ARRAY_SIZE(gpu_cc_sm8150_gdscs),
+};
+
+static const struct of_device_id gpu_cc_sm8150_match_table[] = {
+	{ .compatible = "qcom,sm8150-gpucc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, gpu_cc_sm8150_match_table);
+
+static int gpu_cc_sm8150_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+
+	regmap = qcom_cc_map(pdev, &gpu_cc_sm8150_desc);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
+
+	return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
+}
+
+static struct platform_driver gpu_cc_sm8150_driver = {
+	.probe = gpu_cc_sm8150_probe,
+	.driver = {
+		.name = "sm8150-gpucc",
+		.of_match_table = gpu_cc_sm8150_match_table,
+	},
+};
+
+static int __init gpu_cc_sm8150_init(void)
+{
+	return platform_driver_register(&gpu_cc_sm8150_driver);
+}
+subsys_initcall(gpu_cc_sm8150_init);
+
+static void __exit gpu_cc_sm8150_exit(void)
+{
+	platform_driver_unregister(&gpu_cc_sm8150_driver);
+}
+module_exit(gpu_cc_sm8150_exit);
+
+MODULE_DESCRIPTION("QTI GPUCC SM8150 Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [RESEND PATCH v2 10/13] clk: qcom: Add graphics clock controller driver for SM8250
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (8 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 09/13] clk: qcom: Add graphics clock controller driver for SM8150 Jonathan Marek
@ 2020-06-29 21:17 ` Jonathan Marek
  2020-07-03 15:03 ` [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Dmitry Baryshkov
  10 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-06-29 21:17 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	open list, open list:COMMON CLK FRAMEWORK

Add support for the graphics clock controller found on SM8250
based devices. This would allow graphics drivers to probe and
control their clocks.

This is copied from the downstream kernel, adapted for upstream.
For example, GDSCs have been added.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/Kconfig        |   8 +
 drivers/clk/qcom/Makefile       |   1 +
 drivers/clk/qcom/gpucc-sm8250.c | 450 ++++++++++++++++++++++++++++++++
 3 files changed, 459 insertions(+)
 create mode 100644 drivers/clk/qcom/gpucc-sm8250.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 1bf5e927ee0d..125215e71ec7 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -399,6 +399,14 @@ config SM_GPUCC_8150
 	  Say Y if you want to support graphics controller devices and
 	  functionality such as 3D graphics.
 
+config SM_GPUCC_8250
+	tristate "SM8250 Graphics Clock Controller"
+	select SM_GCC_8250
+	help
+	  Support for the graphics clock controller on SM8250 devices.
+	  Say Y if you want to support graphics controller devices and
+	  functionality such as 3D graphics.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f819663c53a6..b5dcb61af7f2 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
 obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
+obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c
new file mode 100644
index 000000000000..42570fbcdbec
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-sm8250.c
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define CX_GMU_CBCR_SLEEP_MASK		0xf
+#define CX_GMU_CBCR_SLEEP_SHIFT		4
+#define CX_GMU_CBCR_WAKE_MASK		0xf
+#define CX_GMU_CBCR_WAKE_SHIFT		8
+
+enum {
+	P_BI_TCXO,
+	P_CORE_BI_PLL_TEST_SE,
+	P_GPLL0_OUT_MAIN,
+	P_GPLL0_OUT_MAIN_DIV,
+	P_GPU_CC_PLL0_OUT_MAIN,
+	P_GPU_CC_PLL1_OUT_MAIN,
+};
+
+static const struct parent_map gpu_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
+	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
+	{ P_GPLL0_OUT_MAIN, 5 },
+	{ P_GPLL0_OUT_MAIN_DIV, 6 },
+	{ P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gpu_cc_parent_names_0[] = {
+	"bi_tcxo",
+	"gpu_cc_pll0",
+	"gpu_cc_pll1",
+	"gcc_gpu_gpll0_clk_src",
+	"gcc_gpu_gpll0_div_clk_src",
+	"core_bi_pll_test_se",
+};
+
+static struct pll_vco lucid_vco[] = {
+	{ 249600000, 2000000000, 0 },
+};
+
+static const struct alpha_pll_config gpu_cc_pll1_config = {
+	.l = 0x1a,
+	.alpha = 0xaaa,
+	.config_ctl_val = 0x20485699,
+	.config_ctl_hi_val = 0x00002261,
+	.config_ctl_hi1_val = 0x029a699c,
+	.user_ctl_val = 0x00000000,
+	.user_ctl_hi_val = 0x00000805,
+	.user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll gpu_cc_pll1 = {
+	.offset = 0x100,
+	.vco_table = lucid_vco,
+	.num_vco = ARRAY_SIZE(lucid_vco),
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_pll1",
+			.parent_names = (const char *[]){ "bi_tcxo" },
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_lucid_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
+	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
+	.cmd_rcgr = 0x1120,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = gpu_cc_parent_map_0,
+	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gpu_cc_gmu_clk_src",
+		.parent_names = gpu_cc_parent_names_0,
+		.num_parents = 6,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gpu_cc_ahb_clk = {
+	.halt_reg = 0x1078,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x1078,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_crc_ahb_clk = {
+	.halt_reg = 0x107c,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x107c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_crc_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_apb_clk = {
+	.halt_reg = 0x1088,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1088,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_apb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_gmu_clk = {
+	.halt_reg = 0x1098,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1098,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_gmu_clk",
+			.parent_names = (const char *[]){
+				"gpu_cc_gmu_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_qdss_at_clk = {
+	.halt_reg = 0x1080,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1080,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_qdss_at_clk",
+			.parent_names = (const char *[]){
+				"qdss_qmp_clk",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
+	.halt_reg = 0x1094,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1094,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_qdss_trig_clk",
+			.parent_names = (const char *[]){
+				"qdss_qmp_clk",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
+	.halt_reg = 0x1084,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1084,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_qdss_tsctr_clk",
+			.parent_names = (const char *[]){
+				"qdss_qmp_clk",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
+	.halt_reg = 0x108c,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x108c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_snoc_dvm_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cxo_aon_clk = {
+	.halt_reg = 0x1004,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cxo_aon_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cxo_clk = {
+	.halt_reg = 0x109c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x109c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cxo_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_gx_gmu_clk = {
+	.halt_reg = 0x1064,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1064,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_gx_gmu_clk",
+			.parent_names = (const char *[]){
+				"gpu_cc_gmu_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
+	.halt_reg = 0x105c,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x105c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_gx_qdss_tsctr_clk",
+			.parent_names = (const char *[]){
+				"qdss_qmp_clk",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_gx_vsense_clk = {
+	.halt_reg = 0x1058,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_gx_vsense_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_sleep_clk = {
+	.halt_reg = 0x1090,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1090,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_sleep_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
+	.halt_reg = 0x5000,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x5000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
+			 .ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct gdsc gpu_cx_gdsc = {
+	.gdscr = 0x106c,
+	.gds_hw_ctrl = 0x1540,
+	.pd = {
+		.name = "gpu_cx_gdsc",
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = VOTABLE,
+};
+
+static struct gdsc gpu_gx_gdsc = {
+	.gdscr = 0x100c,
+	.clamp_io_ctrl = 0x1508,
+	.pd = {
+		.name = "gpu_gx_gdsc",
+		.power_on = gdsc_gx_do_nothing_enable,
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
+};
+
+static struct clk_regmap *gpu_cc_sm8250_clocks[] = {
+	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
+	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
+	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
+	[GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
+	[GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
+	[GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
+	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
+	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
+	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
+	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
+	[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
+	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
+	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
+	[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
+	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
+};
+
+static const struct qcom_reset_map gpu_cc_sm8250_resets[] = {
+	[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
+	[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
+	[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
+	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
+	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
+	[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
+};
+
+static struct gdsc *gpu_cc_sm8250_gdscs[] = {
+	[GPU_CX_GDSC] = &gpu_cx_gdsc,
+	[GPU_GX_GDSC] = &gpu_gx_gdsc,
+};
+
+static const struct regmap_config gpu_cc_sm8250_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x8008,
+	.fast_io = true,
+};
+
+static const struct qcom_cc_desc gpu_cc_sm8250_desc = {
+	.config = &gpu_cc_sm8250_regmap_config,
+	.clks = gpu_cc_sm8250_clocks,
+	.num_clks = ARRAY_SIZE(gpu_cc_sm8250_clocks),
+	.resets = gpu_cc_sm8250_resets,
+	.num_resets = ARRAY_SIZE(gpu_cc_sm8250_resets),
+	.gdscs = gpu_cc_sm8250_gdscs,
+	.num_gdscs = ARRAY_SIZE(gpu_cc_sm8250_gdscs),
+};
+
+static const struct of_device_id gpu_cc_sm8250_match_table[] = {
+	{ .compatible = "qcom,sm8250-gpucc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, gpu_cc_sm8250_match_table);
+
+static int gpu_cc_sm8250_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+	unsigned int value, mask;
+
+	regmap = qcom_cc_map(pdev, &gpu_cc_sm8250_desc);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
+
+	/*
+	 * Configure gpu_cc_cx_gmu_clk with recommended
+	 * wakeup/sleep settings
+	 */
+	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
+	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
+	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
+	regmap_update_bits(regmap, 0x1098, mask, value);
+
+	return qcom_cc_really_probe(pdev, &gpu_cc_sm8250_desc, regmap);;
+}
+
+static struct platform_driver gpu_cc_sm8250_driver = {
+	.probe = gpu_cc_sm8250_probe,
+	.driver = {
+		.name = "sm8250-gpucc",
+		.of_match_table = gpu_cc_sm8250_match_table,
+	},
+};
+
+static int __init gpu_cc_sm8250_init(void)
+{
+	return platform_driver_register(&gpu_cc_sm8250_driver);
+}
+subsys_initcall(gpu_cc_sm8250_init);
+
+static void __exit gpu_cc_sm8250_exit(void)
+{
+	platform_driver_unregister(&gpu_cc_sm8250_driver);
+}
+module_exit(gpu_cc_sm8250_exit);
+
+MODULE_DESCRIPTION("QTI GPU_CC SM8250 Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.26.1


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings
  2020-06-29 21:17 ` [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings Jonathan Marek
@ 2020-07-02 20:43   ` Rob Herring
  2020-07-02 20:44   ` Rob Herring
  1 sibling, 0 replies; 22+ messages in thread
From: Rob Herring @ 2020-07-02 20:43 UTC (permalink / raw)
  To: Jonathan Marek
  Cc: Michael Turquette, linux-kernel, Andy Gross, linux-arm-msm,
	Rob Herring, linux-clk, devicetree, Stephen Boyd,
	Bjorn Andersson

On Mon, 29 Jun 2020 17:17:12 -0400, Jonathan Marek wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8150 SoCs.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../bindings/clock/qcom,sm8150-gpucc.yaml     | 74 +++++++++++++++++++
>  include/dt-bindings/clock/qcom,gpucc-sm8150.h | 40 ++++++++++
>  2 files changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h
> 


My bot found errors running 'make dt_binding_check' on your patch:

/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml: maintainers:0: None is not of type 'string'
Documentation/devicetree/bindings/Makefile:20: recipe for target 'Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml: ignoring, error in schema: maintainers: 0
warning: no schema found in file: ./Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml: ignoring, error in schema: maintainers: 0
warning: no schema found in file: ./Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
Makefile:1347: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2


See https://patchwork.ozlabs.org/patch/1319320

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:

pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings
  2020-06-29 21:17 ` [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings Jonathan Marek
  2020-07-02 20:43   ` Rob Herring
@ 2020-07-02 20:44   ` Rob Herring
  1 sibling, 0 replies; 22+ messages in thread
From: Rob Herring @ 2020-07-02 20:44 UTC (permalink / raw)
  To: Jonathan Marek
  Cc: linux-arm-msm, Andy Gross, Bjorn Andersson, Michael Turquette,
	Stephen Boyd, open list:COMMON CLK FRAMEWORK,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list

On Mon, Jun 29, 2020 at 05:17:12PM -0400, Jonathan Marek wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8150 SoCs.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../bindings/clock/qcom,sm8150-gpucc.yaml     | 74 +++++++++++++++++++
>  include/dt-bindings/clock/qcom,gpucc-sm8150.h | 40 ++++++++++
>  2 files changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
> new file mode 100644
> index 000000000000..683b50dd3492
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8150-gpucc.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: GPL-2.0-only

Dual license new bindings.

(GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8150-gpucc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Graphics Clock & Reset Controller Binding for SM8150
> +
> +maintainers:
> +  -

Got to pick someone.

> +
> +description: |
> +  Qualcomm graphics clock control module which supports the clocks, resets and
> +  power domains on SM8150.
> +
> +  See also dt-bindings/clock/qcom,gpucc-sm8150.h.
> +
> +properties:
> +  compatible:
> +    const: qcom,sm8150-gpucc
> +
> +  clocks:
> +    items:
> +      - description: Board XO source
> +      - description: GPLL0 main branch source
> +      - description: GPLL0 div branch source
> +
> +  clock-names:
> +    items:
> +      - const: bi_tcxo
> +      - const: gcc_gpu_gpll0_clk_src
> +      - const: gcc_gpu_gpll0_div_clk_src
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  '#power-domain-cells':
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#reset-cells'
> +  - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
> +    #include <dt-bindings/clock/qcom,rpmh.h>
> +    clock-controller@2c90000 {
> +      compatible = "qcom,sm8150-gpucc";
> +      reg = <0x2c90000 0x9000>;
> +      clocks = <&rpmhcc RPMH_CXO_CLK>,
> +               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +      clock-names = "bi_tcxo",
> +                    "gcc_gpu_gpll0_clk_src",
> +                    "gcc_gpu_gpll0_div_clk_src";
> +      #clock-cells = <1>;
> +      #reset-cells = <1>;
> +      #power-domain-cells = <1>;
> +    };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8150.h b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
> new file mode 100644
> index 000000000000..e7cac7fe9739
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
> @@ -0,0 +1,40 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
> +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
> +
> +/* GPU_CC clock registers */
> +#define GPU_CC_AHB_CLK				0
> +#define GPU_CC_CRC_AHB_CLK			1
> +#define GPU_CC_CX_APB_CLK			2
> +#define GPU_CC_CX_GMU_CLK			3
> +#define GPU_CC_CX_QDSS_AT_CLK			4
> +#define GPU_CC_CX_QDSS_TRIG_CLK			5
> +#define GPU_CC_CX_QDSS_TSCTR_CLK		6
> +#define GPU_CC_CX_SNOC_DVM_CLK			7
> +#define GPU_CC_CXO_AON_CLK			8
> +#define GPU_CC_CXO_CLK				9
> +#define GPU_CC_GMU_CLK_SRC			10
> +#define GPU_CC_GX_GMU_CLK			11
> +#define GPU_CC_GX_QDSS_TSCTR_CLK		12
> +#define GPU_CC_GX_VSENSE_CLK			13
> +#define GPU_CC_PLL1				14
> +#define GPU_CC_PLL_TEST_CLK			15
> +#define GPU_CC_SLEEP_CLK			16
> +
> +/* GPU_CC Resets */
> +#define GPUCC_GPU_CC_CX_BCR			0
> +#define GPUCC_GPU_CC_GFX3D_AON_BCR		1
> +#define GPUCC_GPU_CC_GMU_BCR			2
> +#define GPUCC_GPU_CC_GX_BCR			3
> +#define GPUCC_GPU_CC_SPDM_BCR			4
> +#define GPUCC_GPU_CC_XO_BCR			5
> +
> +/* GPU_CC GDSCRs */
> +#define GPU_CX_GDSC				0
> +#define GPU_GX_GDSC				1
> +
> +#endif
> -- 
> 2.26.1
> 

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 07/13] dt-bindings: clock: Introduce SM8250 QCOM Graphics clock bindings
  2020-06-29 21:17 ` [RESEND PATCH v2 07/13] dt-bindings: clock: Introduce SM8250 " Jonathan Marek
@ 2020-07-02 20:46   ` Rob Herring
  2020-07-02 20:49     ` Jonathan Marek
  0 siblings, 1 reply; 22+ messages in thread
From: Rob Herring @ 2020-07-02 20:46 UTC (permalink / raw)
  To: Jonathan Marek
  Cc: linux-arm-msm, Andy Gross, Bjorn Andersson, Michael Turquette,
	Stephen Boyd, open list:COMMON CLK FRAMEWORK,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list

On Mon, Jun 29, 2020 at 05:17:13PM -0400, Jonathan Marek wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8250 SoCs.
> 

Looks like these 2 schemas could be a single one.

> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../bindings/clock/qcom,sm8250-gpucc.yaml     | 74 +++++++++++++++++++
>  include/dt-bindings/clock/qcom,gpucc-sm8250.h | 40 ++++++++++
>  2 files changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
> new file mode 100644
> index 000000000000..2b9c8f97b76d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8250-gpucc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Graphics Clock & Reset Controller Binding for SM8250
> +
> +maintainers:
> +  -
> +
> +description: |
> +  Qualcomm graphics clock control module which supports the clocks, resets and
> +  power domains on SM8250.
> +
> +  See also dt-bindings/clock/qcom,gpucc-sm8250.h.
> +
> +properties:
> +  compatible:
> +    const: qcom,sm8250-gpucc
> +
> +  clocks:
> +    items:
> +      - description: Board XO source
> +      - description: GPLL0 main branch source
> +      - description: GPLL0 div branch source
> +
> +  clock-names:
> +    items:
> +      - const: bi_tcxo
> +      - const: gcc_gpu_gpll0_clk_src
> +      - const: gcc_gpu_gpll0_div_clk_src
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  '#power-domain-cells':
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#reset-cells'
> +  - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
> +    #include <dt-bindings/clock/qcom,rpmh.h>
> +    clock-controller@3d90000 {
> +      compatible = "qcom,sm8250-gpucc";
> +      reg = <0x3d90000 0x9000>;
> +      clocks = <&rpmhcc RPMH_CXO_CLK>,
> +               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +      clock-names = "bi_tcxo",
> +                    "gcc_gpu_gpll0_clk_src",
> +                    "gcc_gpu_gpll0_div_clk_src";
> +      #clock-cells = <1>;
> +      #reset-cells = <1>;
> +      #power-domain-cells = <1>;
> +    };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
> new file mode 100644
> index 000000000000..c8fe64e399fd
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
> @@ -0,0 +1,40 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
> +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
> +
> +/* GPU_CC clock registers */
> +#define GPU_CC_AHB_CLK				0
> +#define GPU_CC_CRC_AHB_CLK			1
> +#define GPU_CC_CX_APB_CLK			2
> +#define GPU_CC_CX_GMU_CLK			3
> +#define GPU_CC_CX_QDSS_AT_CLK			4
> +#define GPU_CC_CX_QDSS_TRIG_CLK			5
> +#define GPU_CC_CX_QDSS_TSCTR_CLK		6
> +#define GPU_CC_CX_SNOC_DVM_CLK			7
> +#define GPU_CC_CXO_AON_CLK			8
> +#define GPU_CC_CXO_CLK				9
> +#define GPU_CC_GMU_CLK_SRC			10
> +#define GPU_CC_GX_GMU_CLK			11
> +#define GPU_CC_GX_QDSS_TSCTR_CLK		12
> +#define GPU_CC_GX_VSENSE_CLK			13
> +#define GPU_CC_PLL1				14
> +#define GPU_CC_SLEEP_CLK			15
> +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		16
> +
> +/* GPU_CC Resets */
> +#define GPUCC_GPU_CC_ACD_BCR			0
> +#define GPUCC_GPU_CC_CX_BCR			1
> +#define GPUCC_GPU_CC_GFX3D_AON_BCR		2
> +#define GPUCC_GPU_CC_GMU_BCR			3
> +#define GPUCC_GPU_CC_GX_BCR			4
> +#define GPUCC_GPU_CC_XO_BCR			5
> +
> +/* GPU_CC GDSCRs */
> +#define GPU_CX_GDSC				0
> +#define GPU_GX_GDSC				1
> +
> +#endif
> -- 
> 2.26.1
> 

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 07/13] dt-bindings: clock: Introduce SM8250 QCOM Graphics clock bindings
  2020-07-02 20:46   ` Rob Herring
@ 2020-07-02 20:49     ` Jonathan Marek
  0 siblings, 0 replies; 22+ messages in thread
From: Jonathan Marek @ 2020-07-02 20:49 UTC (permalink / raw)
  To: Rob Herring
  Cc: linux-arm-msm, Andy Gross, Bjorn Andersson, Michael Turquette,
	Stephen Boyd, open list:COMMON CLK FRAMEWORK,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list

On 7/2/20 4:46 PM, Rob Herring wrote:
> On Mon, Jun 29, 2020 at 05:17:13PM -0400, Jonathan Marek wrote:
>> Add device tree bindings for graphics clock controller for
>> Qualcomm Technology Inc's SM8250 SoCs.
>>
> 
> Looks like these 2 schemas could be a single one.
> 

I agree, but there are already separate schemas for sdm845 and sc7180 
gpucc (which these are a copy paste of), so should those be removed and 
use the single one too?

>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>>   .../bindings/clock/qcom,sm8250-gpucc.yaml     | 74 +++++++++++++++++++
>>   include/dt-bindings/clock/qcom,gpucc-sm8250.h | 40 ++++++++++
>>   2 files changed, 114 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>>   create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>> new file mode 100644
>> index 000000000000..2b9c8f97b76d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>> @@ -0,0 +1,74 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,sm8250-gpucc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Graphics Clock & Reset Controller Binding for SM8250
>> +
>> +maintainers:
>> +  -
>> +
>> +description: |
>> +  Qualcomm graphics clock control module which supports the clocks, resets and
>> +  power domains on SM8250.
>> +
>> +  See also dt-bindings/clock/qcom,gpucc-sm8250.h.
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,sm8250-gpucc
>> +
>> +  clocks:
>> +    items:
>> +      - description: Board XO source
>> +      - description: GPLL0 main branch source
>> +      - description: GPLL0 div branch source
>> +
>> +  clock-names:
>> +    items:
>> +      - const: bi_tcxo
>> +      - const: gcc_gpu_gpll0_clk_src
>> +      - const: gcc_gpu_gpll0_div_clk_src
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  '#reset-cells':
>> +    const: 1
>> +
>> +  '#power-domain-cells':
>> +    const: 1
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - clock-names
>> +  - '#clock-cells'
>> +  - '#reset-cells'
>> +  - '#power-domain-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
>> +    #include <dt-bindings/clock/qcom,rpmh.h>
>> +    clock-controller@3d90000 {
>> +      compatible = "qcom,sm8250-gpucc";
>> +      reg = <0x3d90000 0x9000>;
>> +      clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
>> +               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
>> +      clock-names = "bi_tcxo",
>> +                    "gcc_gpu_gpll0_clk_src",
>> +                    "gcc_gpu_gpll0_div_clk_src";
>> +      #clock-cells = <1>;
>> +      #reset-cells = <1>;
>> +      #power-domain-cells = <1>;
>> +    };
>> +...
>> diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
>> new file mode 100644
>> index 000000000000..c8fe64e399fd
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
>> @@ -0,0 +1,40 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
>> +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
>> +
>> +/* GPU_CC clock registers */
>> +#define GPU_CC_AHB_CLK				0
>> +#define GPU_CC_CRC_AHB_CLK			1
>> +#define GPU_CC_CX_APB_CLK			2
>> +#define GPU_CC_CX_GMU_CLK			3
>> +#define GPU_CC_CX_QDSS_AT_CLK			4
>> +#define GPU_CC_CX_QDSS_TRIG_CLK			5
>> +#define GPU_CC_CX_QDSS_TSCTR_CLK		6
>> +#define GPU_CC_CX_SNOC_DVM_CLK			7
>> +#define GPU_CC_CXO_AON_CLK			8
>> +#define GPU_CC_CXO_CLK				9
>> +#define GPU_CC_GMU_CLK_SRC			10
>> +#define GPU_CC_GX_GMU_CLK			11
>> +#define GPU_CC_GX_QDSS_TSCTR_CLK		12
>> +#define GPU_CC_GX_VSENSE_CLK			13
>> +#define GPU_CC_PLL1				14
>> +#define GPU_CC_SLEEP_CLK			15
>> +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		16
>> +
>> +/* GPU_CC Resets */
>> +#define GPUCC_GPU_CC_ACD_BCR			0
>> +#define GPUCC_GPU_CC_CX_BCR			1
>> +#define GPUCC_GPU_CC_GFX3D_AON_BCR		2
>> +#define GPUCC_GPU_CC_GMU_BCR			3
>> +#define GPUCC_GPU_CC_GX_BCR			4
>> +#define GPUCC_GPU_CC_XO_BCR			5
>> +
>> +/* GPU_CC GDSCRs */
>> +#define GPU_CX_GDSC				0
>> +#define GPU_GX_GDSC				1
>> +
>> +#endif
>> -- 
>> 2.26.1
>>

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
  2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
                   ` (9 preceding siblings ...)
  2020-06-29 21:17 ` [RESEND PATCH v2 10/13] clk: qcom: Add graphics clock controller driver for SM8250 Jonathan Marek
@ 2020-07-03 15:03 ` Dmitry Baryshkov
  2020-07-03 15:08   ` Jonathan Marek
  2020-07-06 19:50   ` Dmitry Baryshkov
  10 siblings, 2 replies; 22+ messages in thread
From: Dmitry Baryshkov @ 2020-07-03 15:03 UTC (permalink / raw)
  To: Jonathan Marek, linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

On 30/06/2020 00:17, Jonathan Marek wrote:
> This series adds the missing clock drivers and dts nodes to enable
> the GPU on both SM8150 and SM8250.
> 
> Note an extra patch [1] is still required for GPU to work on SM8250.
> 
> Changes in V2:
> * Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the newly added
>    SM8150 GPU gcc clocks
> * Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL"
> * Added yaml schemas to gpucc dt-bindings patches
> * Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers" and changed
>    gpucc patches to use it.
> * Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
> * Added missing rpmh regulator level for sm8250 GPU clock levels
> * Use sm8150/sm8250 iommu compatibles in dts
> * Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc clocks in dts
> 
> [1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca

With your patches applied:

[   56.751977] msm msm: [drm:adreno_request_fw] loaded qcom/a650_sqe.fw 
from new location
[   56.760166] msm msm: [drm:adreno_request_fw] loaded qcom/a650_gmu.bin 
from new location
[   56.768485] arm-smmu 3da0000.iommu: genpd_runtime_resume()
[   56.774196] PM: gpu_cx_gdsc: Power-on latency exceeded, new value 
49531 ns
[   56.781730] arm-smmu 3da0000.iommu: resume latency exceeded, 462604 ns
[   56.799559] platform 3d6a000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU 
firmware initialization timed out
[   56.809260] arm-smmu 3da0000.iommu: genpd_runtime_suspend()
[   56.813062] msm msm: [drm:adreno_load_gpu] *ERROR* Couldn't power up 
the GPU: -110


-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
  2020-07-03 15:03 ` [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Dmitry Baryshkov
@ 2020-07-03 15:08   ` Jonathan Marek
  2020-07-03 15:14     ` Dmitry Baryshkov
  2020-07-06 19:50   ` Dmitry Baryshkov
  1 sibling, 1 reply; 22+ messages in thread
From: Jonathan Marek @ 2020-07-03 15:08 UTC (permalink / raw)
  To: Dmitry Baryshkov, linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

On 7/3/20 11:03 AM, Dmitry Baryshkov wrote:
> On 30/06/2020 00:17, Jonathan Marek wrote:
>> This series adds the missing clock drivers and dts nodes to enable
>> the GPU on both SM8150 and SM8250.
>>
>> Note an extra patch [1] is still required for GPU to work on SM8250.
>>
>> Changes in V2:
>> * Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the 
>> newly added
>>    SM8150 GPU gcc clocks
>> * Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove 
>> unused/incorrect PLL_CAL_VAL"
>> * Added yaml schemas to gpucc dt-bindings patches
>> * Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc 
>> drivers" and changed
>>    gpucc patches to use it.
>> * Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
>> * Added missing rpmh regulator level for sm8250 GPU clock levels
>> * Use sm8150/sm8250 iommu compatibles in dts
>> * Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc clocks 
>> in dts
>>
>> [1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca
> 
> With your patches applied:
> 
> [   56.751977] msm msm: [drm:adreno_request_fw] loaded qcom/a650_sqe.fw 
> from new location
> [   56.760166] msm msm: [drm:adreno_request_fw] loaded qcom/a650_gmu.bin 
> from new location
> [   56.768485] arm-smmu 3da0000.iommu: genpd_runtime_resume()
> [   56.774196] PM: gpu_cx_gdsc: Power-on latency exceeded, new value 
> 49531 ns
> [   56.781730] arm-smmu 3da0000.iommu: resume latency exceeded, 462604 ns
> [   56.799559] platform 3d6a000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU 
> firmware initialization timed out
> [   56.809260] arm-smmu 3da0000.iommu: genpd_runtime_suspend()
> [   56.813062] msm msm: [drm:adreno_load_gpu] *ERROR* Couldn't power up 
> the GPU: -110
> 
> 

Do you have your branch published somewhere so I can see what could've 
went wrong?




^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
  2020-07-03 15:08   ` Jonathan Marek
@ 2020-07-03 15:14     ` Dmitry Baryshkov
  2020-07-03 17:29       ` Dmitry Baryshkov
  0 siblings, 1 reply; 22+ messages in thread
From: Dmitry Baryshkov @ 2020-07-03 15:14 UTC (permalink / raw)
  To: Jonathan Marek, linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

On 03/07/2020 18:08, Jonathan Marek wrote:
> On 7/3/20 11:03 AM, Dmitry Baryshkov wrote:
>> On 30/06/2020 00:17, Jonathan Marek wrote:
>>> This series adds the missing clock drivers and dts nodes to enable
>>> the GPU on both SM8150 and SM8250.
>>>
>>> Note an extra patch [1] is still required for GPU to work on SM8250.
>>>
>>> Changes in V2:
>>> * Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the 
>>> newly added
>>>    SM8150 GPU gcc clocks
>>> * Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove 
>>> unused/incorrect PLL_CAL_VAL"
>>> * Added yaml schemas to gpucc dt-bindings patches
>>> * Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc 
>>> drivers" and changed
>>>    gpucc patches to use it.
>>> * Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
>>> * Added missing rpmh regulator level for sm8250 GPU clock levels
>>> * Use sm8150/sm8250 iommu compatibles in dts
>>> * Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc clocks 
>>> in dts
>>>
>>> [1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca
>>
>> With your patches applied:
>>
>> [   56.751977] msm msm: [drm:adreno_request_fw] loaded 
>> qcom/a650_sqe.fw from new location
>> [   56.760166] msm msm: [drm:adreno_request_fw] loaded 
>> qcom/a650_gmu.bin from new location
>> [   56.768485] arm-smmu 3da0000.iommu: genpd_runtime_resume()
>> [   56.774196] PM: gpu_cx_gdsc: Power-on latency exceeded, new value 
>> 49531 ns
>> [   56.781730] arm-smmu 3da0000.iommu: resume latency exceeded, 462604 ns
>> [   56.799559] platform 3d6a000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU 
>> firmware initialization timed out
>> [   56.809260] arm-smmu 3da0000.iommu: genpd_runtime_suspend()
>> [   56.813062] msm msm: [drm:adreno_load_gpu] *ERROR* Couldn't power 
>> up the GPU: -110
>>
>>
> 
> Do you have your branch published somewhere so I can see what could've 
> went wrong?

I've applied your patches (this series + the extra one for gpu/drm/msm) 
on top of 
https://git.linaro.org/landing-teams/working/qualcomm/kernel.git branch 
integration-linux-qcomlt .


-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
  2020-07-03 15:14     ` Dmitry Baryshkov
@ 2020-07-03 17:29       ` Dmitry Baryshkov
  2020-07-05 21:08         ` Jonathan Marek
  0 siblings, 1 reply; 22+ messages in thread
From: Dmitry Baryshkov @ 2020-07-03 17:29 UTC (permalink / raw)
  To: Jonathan Marek, linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

On 03/07/2020 18:14, Dmitry Baryshkov wrote:
> On 03/07/2020 18:08, Jonathan Marek wrote:
>> On 7/3/20 11:03 AM, Dmitry Baryshkov wrote:
>>> On 30/06/2020 00:17, Jonathan Marek wrote:
>>>> This series adds the missing clock drivers and dts nodes to enable
>>>> the GPU on both SM8150 and SM8250.
>>>>
>>>> Note an extra patch [1] is still required for GPU to work on SM8250.
>>>>
>>>> Changes in V2:
>>>> * Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the 
>>>> newly added
>>>>    SM8150 GPU gcc clocks
>>>> * Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove 
>>>> unused/incorrect PLL_CAL_VAL"
>>>> * Added yaml schemas to gpucc dt-bindings patches
>>>> * Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc 
>>>> drivers" and changed
>>>>    gpucc patches to use it.
>>>> * Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
>>>> * Added missing rpmh regulator level for sm8250 GPU clock levels
>>>> * Use sm8150/sm8250 iommu compatibles in dts
>>>> * Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc 
>>>> clocks in dts
>>>>
>>>> [1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca
>>>
>>> With your patches applied:
>>>
>>> [   56.751977] msm msm: [drm:adreno_request_fw] loaded 
>>> qcom/a650_sqe.fw from new location
>>> [   56.760166] msm msm: [drm:adreno_request_fw] loaded 
>>> qcom/a650_gmu.bin from new location
>>> [   56.768485] arm-smmu 3da0000.iommu: genpd_runtime_resume()
>>> [   56.774196] PM: gpu_cx_gdsc: Power-on latency exceeded, new value 
>>> 49531 ns
>>> [   56.781730] arm-smmu 3da0000.iommu: resume latency exceeded, 
>>> 462604 ns
>>> [   56.799559] platform 3d6a000.gmu: [drm:a6xx_gmu_resume] *ERROR* 
>>> GMU firmware initialization timed out
>>> [   56.809260] arm-smmu 3da0000.iommu: genpd_runtime_suspend()
>>> [   56.813062] msm msm: [drm:adreno_load_gpu] *ERROR* Couldn't power 
>>> up the GPU: -110
>>>
>>>
>>
>> Do you have your branch published somewhere so I can see what could've 
>> went wrong?
> 
> I've applied your patches (this series + the extra one for gpu/drm/msm) 
> on top of 
> https://git.linaro.org/landing-teams/working/qualcomm/kernel.git branch 
> integration-linux-qcomlt .

A trimmed down version: 
git.linaro.org/people/dmitry.baryshkov/kernel.git branch sm8250-gpu-test


-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
  2020-07-03 17:29       ` Dmitry Baryshkov
@ 2020-07-05 21:08         ` Jonathan Marek
  2020-07-06 10:28           ` Dmitry Baryshkov
  0 siblings, 1 reply; 22+ messages in thread
From: Jonathan Marek @ 2020-07-05 21:08 UTC (permalink / raw)
  To: Dmitry Baryshkov, linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

On 7/3/20 1:29 PM, Dmitry Baryshkov wrote:
> On 03/07/2020 18:14, Dmitry Baryshkov wrote:
>> On 03/07/2020 18:08, Jonathan Marek wrote:
>>> On 7/3/20 11:03 AM, Dmitry Baryshkov wrote:
>>>> On 30/06/2020 00:17, Jonathan Marek wrote:
>>>>> This series adds the missing clock drivers and dts nodes to enable
>>>>> the GPU on both SM8150 and SM8250.
>>>>>
>>>>> Note an extra patch [1] is still required for GPU to work on SM8250.
>>>>>
>>>>> Changes in V2:
>>>>> * Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the 
>>>>> newly added
>>>>>    SM8150 GPU gcc clocks
>>>>> * Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove 
>>>>> unused/incorrect PLL_CAL_VAL"
>>>>> * Added yaml schemas to gpucc dt-bindings patches
>>>>> * Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc 
>>>>> drivers" and changed
>>>>>    gpucc patches to use it.
>>>>> * Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
>>>>> * Added missing rpmh regulator level for sm8250 GPU clock levels
>>>>> * Use sm8150/sm8250 iommu compatibles in dts
>>>>> * Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc 
>>>>> clocks in dts
>>>>>
>>>>> [1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca
>>>>
>>>> With your patches applied:
>>>>
>>>> [   56.751977] msm msm: [drm:adreno_request_fw] loaded 
>>>> qcom/a650_sqe.fw from new location
>>>> [   56.760166] msm msm: [drm:adreno_request_fw] loaded 
>>>> qcom/a650_gmu.bin from new location
>>>> [   56.768485] arm-smmu 3da0000.iommu: genpd_runtime_resume()
>>>> [   56.774196] PM: gpu_cx_gdsc: Power-on latency exceeded, new value 
>>>> 49531 ns
>>>> [   56.781730] arm-smmu 3da0000.iommu: resume latency exceeded, 
>>>> 462604 ns
>>>> [   56.799559] platform 3d6a000.gmu: [drm:a6xx_gmu_resume] *ERROR* 
>>>> GMU firmware initialization timed out
>>>> [   56.809260] arm-smmu 3da0000.iommu: genpd_runtime_suspend()
>>>> [   56.813062] msm msm: [drm:adreno_load_gpu] *ERROR* Couldn't power 
>>>> up the GPU: -110
>>>>
>>>>
>>>
>>> Do you have your branch published somewhere so I can see what 
>>> could've went wrong?
>>
>> I've applied your patches (this series + the extra one for 
>> gpu/drm/msm) on top of 
>> https://git.linaro.org/landing-teams/working/qualcomm/kernel.git 
>> branch integration-linux-qcomlt .
> 
> A trimmed down version: 
> git.linaro.org/people/dmitry.baryshkov/kernel.git branch sm8250-gpu-test
> 
> 

Hi,

I tried this branch, with only the sm8250-hdk.dts from my other series 
added (USB nodes removed as you don't have those in your branch), and 
the GPU starts up without problems.

Possible differences I can think of:

1) Different firmware version which behaves differently? These are the 
checksums for the firmware I have:

/lib/firmware# md5sum a650_*
f6536ba45c2f9f64ec31438217b6a027  a650_gmu.bin
897be740bed67deaa1943e9c36293165  a650_sqe.fw
00f1b291a2b30c98f05c25506e3f4761  a650_zap.b00
bec0f79c7c6f5b32254facf3c7e046c7  a650_zap.b01
35273e4135147a269076144a3051b498  a650_zap.b02
ce0dd1af27306eb341a01bda642f1c64  a650_zap.elf
09834955a8865073f6ee483f69a98b33  a650_zap.mdt

2) GPU revision is not 650.2 (the downstream driver had workarounds for 
bugs in the first revisions, which I didn't include in the upstream driver)

3) Something in the kernel config is making a difference. Here is the 
kernel config I used to test this: 
https://gist.github.com/flto/c6b1bc48abda6fb580a2f21c51039c81

-Jonathan


^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
  2020-07-05 21:08         ` Jonathan Marek
@ 2020-07-06 10:28           ` Dmitry Baryshkov
  0 siblings, 0 replies; 22+ messages in thread
From: Dmitry Baryshkov @ 2020-07-06 10:28 UTC (permalink / raw)
  To: Jonathan Marek, linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

Hi,

On 06/07/2020 00:08, Jonathan Marek wrote:
> On 7/3/20 1:29 PM, Dmitry Baryshkov wrote:
>> On 03/07/2020 18:14, Dmitry Baryshkov wrote:
>>> On 03/07/2020 18:08, Jonathan Marek wrote:
>>>> On 7/3/20 11:03 AM, Dmitry Baryshkov wrote:
>>>>> On 30/06/2020 00:17, Jonathan Marek wrote:
>>>>>> This series adds the missing clock drivers and dts nodes to enable
>>>>>> the GPU on both SM8150 and SM8250.
>>>>>>
>>>>>> Note an extra patch [1] is still required for GPU to work on SM8250.
>>>>>>
>>>>>> Changes in V2:
>>>>>> * Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the 
>>>>>> newly added
>>>>>>    SM8150 GPU gcc clocks
>>>>>> * Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove 
>>>>>> unused/incorrect PLL_CAL_VAL"
>>>>>> * Added yaml schemas to gpucc dt-bindings patches
>>>>>> * Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc 
>>>>>> drivers" and changed
>>>>>>    gpucc patches to use it.
>>>>>> * Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
>>>>>> * Added missing rpmh regulator level for sm8250 GPU clock levels
>>>>>> * Use sm8150/sm8250 iommu compatibles in dts
>>>>>> * Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc 
>>>>>> clocks in dts
>>>>>>
>>>>>> [1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca
>>>>>
>>>>> With your patches applied:
>>>>>
>>>>> [   56.751977] msm msm: [drm:adreno_request_fw] loaded 
>>>>> qcom/a650_sqe.fw from new location
>>>>> [   56.760166] msm msm: [drm:adreno_request_fw] loaded 
>>>>> qcom/a650_gmu.bin from new location
>>>>> [   56.768485] arm-smmu 3da0000.iommu: genpd_runtime_resume()
>>>>> [   56.774196] PM: gpu_cx_gdsc: Power-on latency exceeded, new 
>>>>> value 49531 ns
>>>>> [   56.781730] arm-smmu 3da0000.iommu: resume latency exceeded, 
>>>>> 462604 ns
>>>>> [   56.799559] platform 3d6a000.gmu: [drm:a6xx_gmu_resume] *ERROR* 
>>>>> GMU firmware initialization timed out
>>>>> [   56.809260] arm-smmu 3da0000.iommu: genpd_runtime_suspend()
>>>>> [   56.813062] msm msm: [drm:adreno_load_gpu] *ERROR* Couldn't 
>>>>> power up the GPU: -110
>>>>>
>>>>>
>>>>
>>>> Do you have your branch published somewhere so I can see what 
>>>> could've went wrong?
>>>
>>> I've applied your patches (this series + the extra one for 
>>> gpu/drm/msm) on top of 
>>> https://git.linaro.org/landing-teams/working/qualcomm/kernel.git 
>>> branch integration-linux-qcomlt .
>>
>> A trimmed down version: 
>> git.linaro.org/people/dmitry.baryshkov/kernel.git branch sm8250-gpu-test
>>
>>
> 
> Hi,
> 
> I tried this branch, with only the sm8250-hdk.dts from my other series 
> added (USB nodes removed as you don't have those in your branch), and 
> the GPU starts up without problems.
> 
> Possible differences I can think of:
> 
> 1) Different firmware version which behaves differently? These are the 
> checksums for the firmware I have:
> 
> /lib/firmware# md5sum a650_*
> f6536ba45c2f9f64ec31438217b6a027  a650_gmu.bin
> 897be740bed67deaa1943e9c36293165  a650_sqe.fw
> 00f1b291a2b30c98f05c25506e3f4761  a650_zap.b00
> bec0f79c7c6f5b32254facf3c7e046c7  a650_zap.b01
> 35273e4135147a269076144a3051b498  a650_zap.b02
> ce0dd1af27306eb341a01bda642f1c64  a650_zap.elf
> 09834955a8865073f6ee483f69a98b33  a650_zap.mdt

Interesting. This is what I have here:

3a3a455289c8c36b97a76b95d1dda5cb  a650_gmu.bin
9439db9b76c84f4aec625ff2bc4d1f90  a650_sqe.fw
00f1b291a2b30c98f05c25506e3f4761  a650_zap.b00
f30017eb17a440476a939d8eb1fbe102  a650_zap.b01
35273e4135147a269076144a3051b498  a650_zap.b02
03cef57e54ff48ab3ad49c7e2bcac56e  a650_zap.elf
93f651f41f4bab30dfb8e2bbd8f64ffd  a650_zap.mdt

> 2) GPU revision is not 650.2 (the downstream driver had workarounds for 
> bugs in the first revisions, which I didn't include in the upstream driver)

Interesting, I will take a look. The first obvious difference is the 
hang timeout and the a6xx_gmu_start() handling.

> 
> 3) Something in the kernel config is making a difference. Here is the 
> kernel config I used to test this: 
> https://gist.github.com/flto/c6b1bc48abda6fb580a2f21c51039c81

No, your config produces the same result:

[   46.964891] msm msm: [drm:0xffffffc01049bd00] loaded qcom/a650_sqe.fw 
from new location
[   46.973156] msm msm: [drm:0xffffffc01049bd00] loaded 
qcom/a650_gmu.bin from new location
[   46.994573] platform 3d6a000.gmu: [drm:0xffffffc0104a85d4] *ERROR* 
GMU firmware initialization timed out
[   47.004537] msm msm: [drm:0xffffffc01049b584] *ERROR* Couldn't power 
up the GPU: -110

-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250
  2020-07-03 15:03 ` [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Dmitry Baryshkov
  2020-07-03 15:08   ` Jonathan Marek
@ 2020-07-06 19:50   ` Dmitry Baryshkov
  1 sibling, 0 replies; 22+ messages in thread
From: Dmitry Baryshkov @ 2020-07-06 19:50 UTC (permalink / raw)
  To: Jonathan Marek, linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
	Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul

On 03/07/2020 18:03, Dmitry Baryshkov wrote:
> On 30/06/2020 00:17, Jonathan Marek wrote:
>> This series adds the missing clock drivers and dts nodes to enable
>> the GPU on both SM8150 and SM8250.
>>
>> Note an extra patch [1] is still required for GPU to work on SM8250.
>>
>> Changes in V2:
>> * Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the 
>> newly added
>>    SM8150 GPU gcc clocks
>> * Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove 
>> unused/incorrect PLL_CAL_VAL"
>> * Added yaml schemas to gpucc dt-bindings patches
>> * Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc 
>> drivers" and changed
>>    gpucc patches to use it.
>> * Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
>> * Added missing rpmh regulator level for sm8250 GPU clock levels
>> * Use sm8150/sm8250 iommu compatibles in dts
>> * Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc clocks 
>> in dts
>>
>> [1] https://gist.github.com/flto/784f1aca761ebf2fe6c105719a4a04ca
> 
> With your patches applied:
> 
> [   56.751977] msm msm: [drm:adreno_request_fw] loaded qcom/a650_sqe.fw 
> from new location
> [   56.760166] msm msm: [drm:adreno_request_fw] loaded qcom/a650_gmu.bin 
> from new location
> [   56.768485] arm-smmu 3da0000.iommu: genpd_runtime_resume()
> [   56.774196] PM: gpu_cx_gdsc: Power-on latency exceeded, new value 
> 49531 ns
> [   56.781730] arm-smmu 3da0000.iommu: resume latency exceeded, 462604 ns
> [   56.799559] platform 3d6a000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU 
> firmware initialization timed out
> [   56.809260] arm-smmu 3da0000.iommu: genpd_runtime_suspend()
> [   56.813062] msm msm: [drm:adreno_load_gpu] *ERROR* Couldn't power up 
> the GPU: -110


Confirmed to be a firmware issue. With older firmware proposed patches 
work fine. A patch to support newer firmware releases will be submitted 
separately.


-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, other threads:[~2020-07-06 19:50 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-29 21:17 [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 01/13] clk: qcom: gcc: fix sm8150 GPU and NPU clocks Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 02/13] clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 03/13] clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 04/13] clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 05/13] clk: qcom: gcc: remove unnecessary vco_table from SM8150 Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 06/13] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings Jonathan Marek
2020-07-02 20:43   ` Rob Herring
2020-07-02 20:44   ` Rob Herring
2020-06-29 21:17 ` [RESEND PATCH v2 07/13] dt-bindings: clock: Introduce SM8250 " Jonathan Marek
2020-07-02 20:46   ` Rob Herring
2020-07-02 20:49     ` Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 08/13] clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 09/13] clk: qcom: Add graphics clock controller driver for SM8150 Jonathan Marek
2020-06-29 21:17 ` [RESEND PATCH v2 10/13] clk: qcom: Add graphics clock controller driver for SM8250 Jonathan Marek
2020-07-03 15:03 ` [RESEND PATCH v2 00/13] Enable GPU for SM8150 and SM8250 Dmitry Baryshkov
2020-07-03 15:08   ` Jonathan Marek
2020-07-03 15:14     ` Dmitry Baryshkov
2020-07-03 17:29       ` Dmitry Baryshkov
2020-07-05 21:08         ` Jonathan Marek
2020-07-06 10:28           ` Dmitry Baryshkov
2020-07-06 19:50   ` Dmitry Baryshkov

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