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From: Matthias Brugger <matthias.bgg@gmail.com>
To: Weiyi Lu <weiyi.lu@mediatek.com>,
	Nicolas Boichat <drinkcat@chromium.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	Fan Chen <fan.chen@mediatek.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-clk@vger.kernel.org, srv_heupstream@mediatek.com,
	stable@vger.kernel.org, Owen Chen <owen.chen@mediatek.com>,
	Mars Cheng <mars.cheng@mediatek.com>
Subject: Re: [PATCH v4 04/12] soc: mediatek: add new flow for mtcmos power.
Date: Fri, 8 Feb 2019 19:30:40 +0100
Message-ID: <af929b5d-ff93-f7b2-bf32-66539cde2bd5@gmail.com> (raw)
In-Reply-To: <20190201083016.25856-6-weiyi.lu@mediatek.com>



On 01/02/2019 09:30, Weiyi Lu wrote:
> From: Owen Chen <owen.chen@mediatek.com>
> 
> Both MT8183 & MT6765 add more bus protect node than previous project,
> therefore we add two more register for setup bus protect, which reside
> at INFRA_CFG & SMI_COMMON.
> 
> With the following change
> 1. bus protect need not only infracfg but smi_common registers involved
>    to setup. Therefore we add a set/clr APIs with more customize arguments.
> 
> The second change is that we also add subsys CG control flow before/after
> the bus protect/sram control, due to bus protect need SMI bus relative CGs
> enable to feed-back its ack, and some master's sram control need CG enable
> to on/off its resource sequentially.
> 
> With the following change
> 1. turn on subsys CG before sram pwron and release bus protect.
> 2. turn off subsys CG after the process of set bus protect/receive
>    ack/disable sram.
> 
> The last change is for some power domains like vpu_core on MT8183 whose
> sram need to do clock and internal isolation while power on/off sram.
> We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to
> do the extra sram isolation control or not.
> 

This commit message indicates that you can and should put this changes in
several patches. This will make it easier to understand what you are doing and
and the reason why you are doing it.

> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
>  drivers/soc/mediatek/Makefile           |   2 +-
>  drivers/soc/mediatek/mtk-scpsys-ext.c   |  99 +++++++
>  drivers/soc/mediatek/mtk-scpsys.c       | 376 ++++++++++++++++++------
>  include/linux/soc/mediatek/scpsys-ext.h |  39 +++
>  4 files changed, 428 insertions(+), 88 deletions(-)
>  create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
>  create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
> 
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 64ce5eeaba32..b9dbad6b12f9 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,4 +1,4 @@
>  obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
> new file mode 100644
> index 000000000000..f630edb2f65d
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <Owen.Chen@mediatek.com>
> + */
> +#include <linux/ktime.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/mediatek/scpsys-ext.h>
> +
> +#define MTK_POLL_DELAY_US   10
> +#define MTK_POLL_TIMEOUT    USEC_PER_SEC
> +
> +static int set_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
> +		u32 reg_set, u32 reg_sta, u32 reg_en)

why can't we just use this function for all accesses and get rid of the
mtk_infracfg_set_bus_protection?

> +{
> +	u32 val;
> +
> +	if (reg_set)

just use one variable reg and add a boolean stating if you need write or update.
Might make sense to pass a struct here to not bloat the function parameters.


> +		regmap_write(map, reg_set, mask);
> +	else
> +		regmap_update_bits(map, reg_en, mask, mask);
> +
> +	return regmap_read_poll_timeout(map, reg_sta,
> +			val, (val & ack_mask) == ack_mask,
> +			MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> +}
> +
> +static int clear_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
> +		u32 reg_clr, u32 reg_sta, u32 reg_en)
> +{
> +	u32 val;
> +
> +	if (reg_clr)
> +		regmap_write(map, reg_clr, mask);
> +	else
> +		regmap_update_bits(map, reg_en, mask, 0);
> +
> +	return regmap_read_poll_timeout(map, reg_sta,
> +			val, !(val & ack_mask),
> +			MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> +}
> +
> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> +	struct regmap *infracfg, struct regmap *smi_common)
> +{
> +	int i;
> +
> +	for (i = 0; i < MAX_STEPS && bp_table[i].mask; i++) {

I'd prefer to pass the number of entries in bp_table here. In any case check for
the mask is somehow confusing.
The use of bp_table[i] many times allows to create a local pointer to point to
the entry.

> +		struct regmap *map;
> +		int ret;
> +
> +		if (bp_table[i].type == IFR_TYPE)
> +			map = infracfg;
> +		else if (bp_table[i].type == SMI_TYPE)
> +			map = smi_common;
> +		else
> +			return -EINVAL;
> +
> +		ret = set_bus_protection(map,
> +				bp_table[i].mask, bp_table[i].mask,
> +				bp_table[i].set_ofs, bp_table[i].sta_ofs,
> +				bp_table[i].en_ofs);
> +
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> +	struct regmap *infracfg, struct regmap *smi_common)
> +{
> +	int i;
> +
> +	for (i = MAX_STEPS - 1; i >= 0; i--) {
> +		struct regmap *map;
> +		int ret;
> +
> +		if (bp_table[i].type == IFR_TYPE)
> +			map = infracfg;
> +		else if (bp_table[i].type == SMI_TYPE)
> +			map = smi_common;
> +		else
> +			return -EINVAL;
> +
> +		ret = clear_bus_protection(map,
> +				bp_table[i].mask, bp_table[i].clr_ack_mask,
> +				bp_table[i].clr_ofs, bp_table[i].sta_ofs,
> +				bp_table[i].en_ofs);
> +
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 5b24bb4bfbf6..53a16fa327cf 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -1,15 +1,7 @@
> -/*
> - * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> +

extra patch please.

>  #include <linux/clk.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> @@ -20,6 +12,7 @@
>  #include <linux/pm_domain.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/soc/mediatek/infracfg.h>
> +#include <linux/soc/mediatek/scpsys-ext.h>
>  
>  #include <dt-bindings/power/mt2701-power.h>
>  #include <dt-bindings/power/mt2712-power.h>
> @@ -29,7 +22,7 @@
>  #include <dt-bindings/power/mt8173-power.h>
>  
>  #define MTK_POLL_DELAY_US   10
> -#define MTK_POLL_TIMEOUT    (jiffies_to_usecs(HZ))
> +#define MTK_POLL_TIMEOUT    USEC_PER_SEC
>  
>  #define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)
>  #define MTK_SCPD_FWAIT_SRAM		BIT(1)
> @@ -64,6 +57,8 @@
>  #define PWR_ON_BIT			BIT(2)
>  #define PWR_ON_2ND_BIT			BIT(3)
>  #define PWR_CLK_DIS_BIT			BIT(4)
> +#define PWR_SRAM_CLKISO_BIT		BIT(5)
> +#define PWR_SRAM_ISOINT_B_BIT		BIT(6)
>  
>  #define PWR_STATUS_CONN			BIT(1)
>  #define PWR_STATUS_DISP			BIT(3)
> @@ -115,16 +110,40 @@ static const char * const clk_names[] = {
>  };
>  
>  #define MAX_CLKS	3
> -
> +#define MAX_SUBSYS_CLKS 10
> +
> +/**
> + * struct scp_domain_data - scp domain data for power on/off flow
> + * @name: The domain name.
> + * @sta_mask: The mask for power on/off status bit.
> + * @ctl_offs: The offset for main power control register.
> + * @sram_iso_ctrl: The flag to judge if the power domain need to do
> + *                 the extra sram isolation control.
> + * @sram_pdn_bits: The mask for sram power control bits.
> + * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> + * @bus_prot_mask: The mask for single step bus protection.
> + * @clk_id: The basic clock needs to be enabled before enabling certain
> + *          power domains.
> + * @basic_clk_name: provide the same purpose with field "clk_id"
> + *                  by declaring basic clock prefix name rather than clk_id.
> + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
> + *                     before releasing bus protection.
> + * @caps: The flag for active wake-up action.
> + * @bp_table: The mask table for multiple step bus protection.
> + */
>  struct scp_domain_data {
>  	const char *name;
>  	u32 sta_mask;
>  	int ctl_offs;
> +	bool sram_iso_ctrl;
>  	u32 sram_pdn_bits;
>  	u32 sram_pdn_ack_bits;
>  	u32 bus_prot_mask;
>  	enum clk_id clk_id[MAX_CLKS];
> +	const char *basic_clk_name[MAX_CLKS];

it is not explained in the commit message why we would need the name here.

> +	const char *subsys_clk_prefix;
>  	u8 caps;
> +	struct bus_prot bp_table[MAX_STEPS];
>  };
>  
>  struct scp;
> @@ -133,6 +152,7 @@ struct scp_domain {
>  	struct generic_pm_domain genpd;
>  	struct scp *scp;
>  	struct clk *clk[MAX_CLKS];
> +	struct clk *subsys_clk[MAX_SUBSYS_CLKS];
>  	const struct scp_domain_data *data;
>  	struct regulator *supply;
>  };
> @@ -148,6 +168,7 @@ struct scp {
>  	struct device *dev;
>  	void __iomem *base;
>  	struct regmap *infracfg;
> +	struct regmap *smi_common;
>  	struct scp_ctrl_reg ctrl_reg;
>  	bool bus_prot_reg_update;
>  };
> @@ -188,32 +209,166 @@ static int scpsys_domain_is_on(struct scp_domain *scpd)
>  	return -EINVAL;
>  }
>  
> +static int scpsys_regulator_enable(struct scp_domain *scpd)
> +{
> +	if (!scpd->supply)
> +		return 0;
> +
> +	return regulator_enable(scpd->supply);
> +}
> +
> +static int scpsys_regulator_disable(struct scp_domain *scpd)
> +{
> +	if (!scpd->supply)
> +		return 0;
> +
> +	return regulator_disable(scpd->supply);
> +}
> +
> +static int scpsys_clk_enable(struct clk *clk[], int max_num)

introducing the clock refactoring should be a seperate patch.

> +{
> +	int i, ret = 0;
> +
> +	for (i = 0; i < max_num && clk[i]; i++) {
> +		ret = clk_prepare_enable(clk[i]);
> +		if (ret) {
> +			for (--i; i >= 0; i--)
> +				clk_disable_unprepare(clk[i]);
> +
> +			break;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static int scpsys_clk_disable(struct clk *clk[], int max_num)
> +{
> +	int i;
> +
> +	for (i = max_num - 1; i >= 0; i--) {
> +		if (clk[i])
> +			clk_disable_unprepare(clk[i]);
> +	}
> +
> +	return 0;
> +}
> +
> +static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)

make all the refactoring an extra patch where you just do that without any
logical change.

> +{
> +	u32 val;
> +	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> +	int tmp;
> +
> +	val = readl(ctl_addr) & ~scpd->data->sram_pdn_bits;
> +	writel(val, ctl_addr);
> +
> +	/* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
> +	if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
> +		/*
> +		 * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
> +		 * MT7622_POWER_DOMAIN_WB and thus just a trivial setup
> +		 * is applied here.
> +		 */
> +		usleep_range(12000, 12100);
> +	} else {
> +		/* Either wait until SRAM_PDN_ACK all 1 or 0 */
> +		int ret = readl_poll_timeout(ctl_addr, tmp,
> +				(tmp & pdn_ack) == 0,
> +				MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	if (scpd->data->sram_iso_ctrl)	{
> +		val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
> +		writel(val, ctl_addr);
> +		udelay(1);
> +		val &= ~PWR_SRAM_CLKISO_BIT;
> +		writel(val, ctl_addr);
> +	}
> +
> +	return 0;
> +}
> +
> +static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
> +{
> +	u32 val;
> +	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> +	int tmp;
> +
> +	if (scpd->data->sram_iso_ctrl)	{
> +		val = readl(ctl_addr);
> +		val |= PWR_SRAM_CLKISO_BIT;
> +		writel(val, ctl_addr);
> +		val &= ~PWR_SRAM_ISOINT_B_BIT;
> +		writel(val, ctl_addr);
> +		udelay(1);
> +	}
> +
> +	val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
> +	writel(val, ctl_addr);
> +
> +	/* Either wait until SRAM_PDN_ACK all 1 or 0 */
> +	return readl_poll_timeout(ctl_addr, tmp,
> +			(tmp & pdn_ack) == pdn_ack,
> +			MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> +}
> +
> +static int scpsys_bus_protect_enable(struct scp_domain *scpd)
> +{
> +	struct scp *scp = scpd->scp;
> +	int ret = 0;
> +
> +	if (scpd->data->bus_prot_mask) {
> +		ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> +				scpd->data->bus_prot_mask,
> +				scp->bus_prot_reg_update);
> +	} else if (scpd->data->bp_table[0].mask) {
> +		ret = mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
> +				scp->infracfg,
> +				scp->smi_common);

Please change all existing domains with a bus_prot_mask to use a bp_table with
one entry. I suppose one patch would be adding the bp_table infrastructure and
following one will change all domains. Just have a look what is more elegant.

> +	}
> +
> +	return ret;
> +}
> +
> +static int scpsys_bus_protect_disable(struct scp_domain *scpd)
> +{
> +	struct scp *scp = scpd->scp;
> +	int ret = 0;
> +
> +	if (scpd->data->bus_prot_mask) {
> +		ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> +				scpd->data->bus_prot_mask,
> +				scp->bus_prot_reg_update);
> +	} else if (scpd->data->bp_table[0].mask) {
> +		ret = mtk_scpsys_ext_clear_bus_protection(
> +				scpd->data->bp_table,
> +				scp->infracfg,
> +				scp->smi_common);
> +	}
> +
> +	return ret;
> +}
> +
>  static int scpsys_power_on(struct generic_pm_domain *genpd)
>  {
>  	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
>  	struct scp *scp = scpd->scp;
>  	void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
> -	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
>  	u32 val;
>  	int ret, tmp;
> -	int i;
>  
> -	if (scpd->supply) {
> -		ret = regulator_enable(scpd->supply);
> -		if (ret)
> -			return ret;
> -	}
> -
> -	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
> -		ret = clk_prepare_enable(scpd->clk[i]);
> -		if (ret) {
> -			for (--i; i >= 0; i--)
> -				clk_disable_unprepare(scpd->clk[i]);
> +	ret = scpsys_regulator_enable(scpd);
> +	if (ret < 0)
> +		return ret;
>  
> -			goto err_clk;
> -		}
> -	}
> +	ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
> +	if (ret)
> +		goto err_clk;
>  
> +	/* subsys power on */
>  	val = readl(ctl_addr);
>  	val |= PWR_ON_BIT;
>  	writel(val, ctl_addr);
> @@ -235,43 +390,26 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
>  	val |= PWR_RST_B_BIT;
>  	writel(val, ctl_addr);
>  
> -	val &= ~scpd->data->sram_pdn_bits;
> -	writel(val, ctl_addr);
> -
> -	/* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
> -	if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
> -		/*
> -		 * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
> -		 * MT7622_POWER_DOMAIN_WB and thus just a trivial setup is
> -		 * applied here.
> -		 */
> -		usleep_range(12000, 12100);
> +	ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> +	if (ret < 0)
> +		goto err_pwr_ack;

in between all this refactoring it is difficult to find the relevant change, so
please try to think about the maintainer when doing changes to the code base, as
he has to understand and accept (hopefully in this order ;) your code.

>  
> -	} else {
> -		ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
> -					 MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> -		if (ret < 0)
> -			goto err_pwr_ack;
> -	}
> +	ret = scpsys_sram_enable(scpd, ctl_addr);
> +	if (ret < 0)
> +		goto err_sram;
>  
> -	if (scpd->data->bus_prot_mask) {
> -		ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
> -				scpd->data->bus_prot_mask,
> -				scp->bus_prot_reg_update);
> -		if (ret)
> -			goto err_pwr_ack;
> -	}
> +	ret = scpsys_bus_protect_disable(scpd);
> +	if (ret < 0)
> +		goto err_sram;
>  
>  	return 0;
>  
> +err_sram:
> +	scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>  err_pwr_ack:
> -	for (i = MAX_CLKS - 1; i >= 0; i--) {
> -		if (scpd->clk[i])
> -			clk_disable_unprepare(scpd->clk[i]);
> -	}
> +	scpsys_clk_disable(scpd->clk, MAX_CLKS);
>  err_clk:
> -	if (scpd->supply)
> -		regulator_disable(scpd->supply);
> +	scpsys_regulator_disable(scpd);
>  
>  	dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
>  
> @@ -283,29 +421,21 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>  	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
>  	struct scp *scp = scpd->scp;
>  	void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
> -	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
>  	u32 val;
>  	int ret, tmp;
> -	int i;
> -
> -	if (scpd->data->bus_prot_mask) {
> -		ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> -				scpd->data->bus_prot_mask,
> -				scp->bus_prot_reg_update);
> -		if (ret)
> -			goto out;
> -	}
>  
> -	val = readl(ctl_addr);
> -	val |= scpd->data->sram_pdn_bits;
> -	writel(val, ctl_addr);
> +	ret = scpsys_bus_protect_enable(scpd);
> +	if (ret < 0)
> +		goto out;
>  
> -	/* wait until SRAM_PDN_ACK all 1 */
> -	ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
> -				 MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> +	ret = scpsys_sram_disable(scpd, ctl_addr);
>  	if (ret < 0)
>  		goto out;
>  
> +	ret = scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> +
> +	/* subsys power off */
> +	val = readl(ctl_addr);
>  	val |= PWR_ISO_BIT;
>  	writel(val, ctl_addr);
>  
> @@ -327,11 +457,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>  	if (ret < 0)
>  		goto out;
>  
> -	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
> -		clk_disable_unprepare(scpd->clk[i]);
> +	scpsys_clk_disable(scpd->clk, MAX_CLKS);
>  
> -	if (scpd->supply)
> -		regulator_disable(scpd->supply);
> +	scpsys_regulator_disable(scpd);
>  
>  	return 0;
>  
> @@ -341,6 +469,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>  	return ret;
>  }
>  
> +static int init_subsys_clks(struct platform_device *pdev,
> +		const char *prefix, struct clk **clk)
> +{
> +	struct device_node *node = pdev->dev.of_node;
> +	u32 prefix_len, sub_clk_cnt = 0;
> +	struct property *prop;
> +	const char *clk_name;
> +
> +	if (!node) {
> +		dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
> +			PTR_ERR(node));
> +		return PTR_ERR(node);
> +	}

You are changing the way the devicetree node looks like, please add a patch
adding the information to the binding.

> +
> +	prefix_len = strlen(prefix);
> +
> +	of_property_for_each_string(node, "clock-names", prop, clk_name) {
> +		if (!strncmp(clk_name, prefix, prefix_len) &&
> +				(clk_name[prefix_len] == '-')) {
> +			if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
> +				dev_err(&pdev->dev,
> +					"subsys clk out of range %d\n",
> +					sub_clk_cnt);
> +				return -ENOMEM;

ENOMEM?

> +			}
> +
> +			clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
> +						clk_name);
> +

to be honest I'm not sure what you are doing here. You are creating the clock
names to get them from the CCF, but why can't you use some of_clk_get* accessors?

> +			if (IS_ERR(clk)) {
> +				dev_err(&pdev->dev,
> +					"Subsys clk read fail %ld\n",
> +					PTR_ERR(clk));
> +				return PTR_ERR(clk);
> +			}
> +			sub_clk_cnt++;
> +		}
> +	}
> +
> +	return sub_clk_cnt;
> +}
> +
>  static void init_clks(struct platform_device *pdev, struct clk **clk)
>  {
>  	int i;
> @@ -396,6 +566,17 @@ static struct scp *init_scp(struct platform_device *pdev,
>  		return ERR_CAST(scp->infracfg);
>  	}
>  
> +	scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +			"smi_comm");
> +
> +	if (scp->smi_common == ERR_PTR(-ENODEV)) {
> +		scp->smi_common = NULL;
> +	} else if (IS_ERR(scp->smi_common)) {

if error:
  if it's ENODEV:
    set smi_common to NULL
  else: error out.

> +		dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
> +				PTR_ERR(scp->smi_common));
> +		return ERR_CAST(scp->smi_common);
> +	}
> +
>  	for (i = 0; i < num; i++) {
>  		struct scp_domain *scpd = &scp->domains[i];
>  		const struct scp_domain_data *data = &scp_domain_data[i];
> @@ -417,22 +598,43 @@ static struct scp *init_scp(struct platform_device *pdev,
>  		struct scp_domain *scpd = &scp->domains[i];
>  		struct generic_pm_domain *genpd = &scpd->genpd;
>  		const struct scp_domain_data *data = &scp_domain_data[i];
> +		int clk_cnt;
>  
>  		pd_data->domains[i] = genpd;
>  		scpd->scp = scp;
>  
>  		scpd->data = data;
>  
> -		for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> -			struct clk *c = clk[data->clk_id[j]];
> +		if (data->clk_id[0]) {
> +			for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> +				struct clk *c = clk[data->clk_id[j]];
>  
> -			if (IS_ERR(c)) {
> -				dev_err(&pdev->dev, "%s: clk unavailable\n",
> -					data->name);
> -				return ERR_CAST(c);
> +				if (IS_ERR(c)) {
> +					dev_err(&pdev->dev,
> +						"%s: clk unavailable\n",
> +						data->name);
> +					return ERR_CAST(c);
> +				}
> +
> +				scpd->clk[j] = c;
>  			}
> +		} else if (data->basic_clk_name[0]) {
> +			for (j = 0; j < MAX_CLKS &&
> +					data->basic_clk_name[j]; j++)
> +				scpd->clk[j] = devm_clk_get(&pdev->dev,
> +						data->basic_clk_name[j]);
> +		}

You have to explain why we need this basic clocks and why we can't get them in
init_clk

Regards,
Matthias


>  
> -			scpd->clk[j] = c;
> +		if (data->subsys_clk_prefix) {
> +			clk_cnt = init_subsys_clks(pdev,
> +					data->subsys_clk_prefix,
> +					scpd->subsys_clk);
> +			if (clk_cnt < 0) {
> +				dev_err(&pdev->dev,
> +					"%s: subsys clk unavailable\n",
> +					data->name);
> +				return ERR_PTR(clk_cnt);
> +			}
>  		}
>  
>  		genpd->name = data->name;
> diff --git a/include/linux/soc/mediatek/scpsys-ext.h b/include/linux/soc/mediatek/scpsys-ext.h
> new file mode 100644
> index 000000000000..d0ed295c88a7
> --- /dev/null
> +++ b/include/linux/soc/mediatek/scpsys-ext.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
> +#define __SOC_MEDIATEK_SCPSYS_EXT_H
> +
> +#define MAX_STEPS	4
> +
> +#define BUS_PROT(_type, _set_ofs, _clr_ofs,			\
> +		_en_ofs, _sta_ofs, _mask, _clr_ack_mask) {	\
> +		.type = _type,					\
> +		.set_ofs = _set_ofs,				\
> +		.clr_ofs = _clr_ofs,				\
> +		.en_ofs = _en_ofs,				\
> +		.sta_ofs = _sta_ofs,				\
> +		.mask = _mask,					\
> +		.clr_ack_mask = _clr_ack_mask,			\
> +	}
> +
> +enum regmap_type {
> +	IFR_TYPE,
> +	SMI_TYPE,
> +	MAX_REGMAP_TYPE,
> +};
> +
> +struct bus_prot {
> +	enum regmap_type type;
> +	u32 set_ofs;
> +	u32 clr_ofs;
> +	u32 en_ofs;
> +	u32 sta_ofs;
> +	u32 mask;
> +	u32 clr_ack_mask;
> +};
> +
> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> +	struct regmap *infracfg, struct regmap *smi_common);
> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> +	struct regmap *infracfg, struct regmap *smi_common);
> +
> +#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
> 

  reply index

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-01  8:30 [PATCH v4 00/12] Mediatek MT8183 clock and scpsys support Weiyi Lu
2019-02-01  8:30 ` Weiyi Lu
2019-02-20 19:18   ` Stephen Boyd
2019-02-21  8:36     ` Matthias Brugger
2019-02-22  7:48       ` Stephen Boyd
2019-02-26  4:00         ` Weiyi Lu
2019-02-26 17:45           ` Stephen Boyd
2019-02-01  8:30 ` [PATCH v4 01/12] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu
2019-02-26 15:59   ` Matthias Brugger
2019-02-27  3:51     ` Weiyi Lu
2019-02-27  4:39       ` Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 02/12] clk: mediatek: add new clkmux register API Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 04/12] soc: mediatek: add new flow for mtcmos power Weiyi Lu
2019-02-08 18:30   ` Matthias Brugger [this message]
2019-02-01  8:30 ` [PATCH v4 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 07/12] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 08/12] clk: mediatek: Add MT8183 clock support Weiyi Lu
2019-02-26 17:50   ` Stephen Boyd
2019-02-27  2:51     ` Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu
2019-02-07 15:35   ` Matthias Brugger
2019-02-01  8:30 ` [PATCH v4 10/12] dt-bindings: soc: Add MT8183 " Weiyi Lu
2019-02-08 18:33   ` Matthias Brugger
2019-02-01  8:30 ` [PATCH v4 11/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-02-01  8:30 ` [PATCH v4 12/12] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu

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