From: Jianxin Pan <jianxin.pan@amlogic.com>
To: Stephen Boyd <sboyd@kernel.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: Yixun Lan <yixun.lan@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Carlo Caione <carlo@caione.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Boris Brezillon <boris.brezillon@bootlin.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Liang Yang <liang.yang@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Hanjie Lin <hanjie.lin@amlogic.com>,
Victor Wan <victor.wan@amlogic.com>, <linux-clk@vger.kernel.org>,
<linux-amlogic@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v7 2/4] clk: meson: add DT documentation for emmc clock controller
Date: Tue, 4 Dec 2018 10:39:34 +0800 [thread overview]
Message-ID: <b401f5bc-32e7-1693-0839-87ffa3dd5767@amlogic.com> (raw)
In-Reply-To: <154387713374.88331.16436869339024592009@swboyd.mtv.corp.google.com>
Hi Stephen,
On 2018/12/4 6:45, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-11-15 04:18:30)
>> diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h b/include/dt-bindings/clock/amlogic,mmc-clkc.h
>> new file mode 100644
>> index 0000000..162b949
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
>> @@ -0,0 +1,17 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Meson MMC sub clock tree IDs
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Yixun Lan <yixun.lan@amlogic.com>
>> + */
>> +
>> +#ifndef __MMC_CLKC_H
>> +#define __MMC_CLKC_H
>> +
>> +#define CLKID_MMC_DIV 1
>
> Why does the define numbering start with 1 instead of 0?
>
The Clock ID 0 is used by CLKID_MMC_MUX.
CLKID_MMC_MUX is an internal clock which defined in drivers/clk/meson/mmc-clkc.c, and it's the parent of CLKID_MMC_DIV.
>> +#define CLKID_MMC_PHASE_CORE 2
>> +#define CLKID_MMC_PHASE_TX 3
>> +#define CLKID_MMC_PHASE_RX 4
>> +
>
> .
>
next prev parent reply other threads:[~2018-12-04 2:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-15 12:18 [PATCH v7 0/4] clk: meson: add a sub EMMC clock controller support Jianxin Pan
2018-11-15 12:18 ` [PATCH v7 1/4] clk: meson: add emmc sub clock phase delay driver Jianxin Pan
2018-11-15 12:18 ` [PATCH v7 2/4] clk: meson: add DT documentation for emmc clock controller Jianxin Pan
2018-12-03 22:45 ` Stephen Boyd
2018-12-04 2:39 ` Jianxin Pan [this message]
2018-12-04 19:25 ` Stephen Boyd
2018-11-15 12:18 ` [PATCH v7 3/4] clk: meson: add sub MMC clock controller driver Jianxin Pan
2018-11-15 12:18 ` [PATCH v7 4/4] clk: meson: add one based divider support for sclk divider Jianxin Pan
2018-11-29 1:48 ` [PATCH v7 0/4] clk: meson: add a sub EMMC clock controller support Jianxin Pan
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