From: Yu Tu <yu.tu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: kelvin.zhang@amlogic.com, qi.duan@amlogic.com
Subject: Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
Date: Thu, 8 Jun 2023 17:30:52 +0800 [thread overview]
Message-ID: <b502cbf7-40a1-6041-f535-54651cfd9874@amlogic.com> (raw)
In-Reply-To: <1jttvi9vnq.fsf@starbuckisacylon.baylibre.com>
On 2023/6/8 16:53, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
>>>> +
>>>> +static struct clk_regmap s4_fclk_div4 = {
>>>> + .data = &(struct clk_regmap_gate_data){
>>>> + .offset = ANACTRL_FIXPLL_CTRL1,
>>>> + .bit_idx = 21,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "fclk_div4",
>>>> + /*
>>>> + * For more information, please refer to s4_fixed_pll_dco.
>>>> + */
>>> While div2 and div3 got an explanation from previous SoCs, they others -
>>> like div4/div7/etc ... - have been able to cope with rw ops so far.
>>> Why is the S4 different for all these clocks ?
>>
>> The chip was changed fixed pll for security reasons.
>>
>> Fixed PLL registers are not writable in the kernel phase. Write of fixed
>> PLL-related register will cause the system to crash.
>>
>
> That is definitely worth mentionning
Can I understand that you agree with the use of "ro_ops" for FIXed PLL
related clocks later?
>
>>> Requiring RO ops (or fishy clock flags) is usually a sign that a clock
>>> is used without an appropriate driver.
>>>
>
> Neil is currently dealing with the dt-bindings, please
> * Adjust your patchset accordingly
> * Wait for his v2 to land, you'll need it.
OKay.
>
>>>> + .ops = &clk_regmap_gate_ro_ops,
>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>> + &s4_fclk_div4_div.hw
>>>> + },
>>>> + .num_parents = 1,
>>>> + },
>>>> +};
>>>> +
next prev parent reply other threads:[~2023-06-08 9:31 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 7:02 [PATCH V9 0/4] Add S4 SoC PLL and Peripheral clock Yu Tu
2023-05-17 7:02 ` [PATCH V9 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller Yu Tu
2023-05-17 7:02 ` [PATCH V9 2/4] dt-bindings: clock: document Amlogic S4 SoC peripherals " Yu Tu
2023-05-17 7:02 ` [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
2023-06-06 14:02 ` Jerome Brunet
2023-06-08 2:54 ` Yu Tu
2023-06-08 8:53 ` Jerome Brunet
2023-06-08 9:30 ` Yu Tu [this message]
2023-06-08 11:32 ` Dmitry Rokosov
2023-06-08 12:46 ` Jerome Brunet
2023-06-08 21:02 ` Dmitry Rokosov
2023-06-06 14:34 ` Jerome Brunet
2023-06-08 2:29 ` Yu Tu
[not found] ` <20230517070215.28463-5-yu.tu@amlogic.com>
[not found] ` <1jwn0g39t2.fsf@starbuckisacylon.baylibre.com>
2023-06-06 15:38 ` [PATCH V9 4/4] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller Dmitry Rokosov
2023-06-08 3:26 ` Yu Tu
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