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Mon, 3 Oct 2022 18:47:07 GMT Received: from [10.110.93.213] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 3 Oct 2022 11:47:05 -0700 Message-ID: Date: Mon, 3 Oct 2022 13:47:05 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Content-Language: en-US To: Krzysztof Kozlowski , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner , Marc Zyngier CC: , , , References: <20221001030403.27659-1-quic_molvera@quicinc.com> <20221001030403.27659-2-quic_molvera@quicinc.com> <37926f0f-e176-929e-939a-cd43a031e224@linaro.org> From: Melody Olvera In-Reply-To: <37926f0f-e176-929e-939a-cd43a031e224@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xfMCvX5q60oCKiMGzugQKRSsdKD40Brv X-Proofpoint-ORIG-GUID: xfMCvX5q60oCKiMGzugQKRSsdKD40Brv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-03_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 clxscore=1011 malwarescore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210030112 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 10/1/2022 4:24 AM, Krzysztof Kozlowski wrote: > On 01/10/2022 05:03, Melody Olvera wrote: >> Add device tree bindings for global clock controller on QDU1000 and >> QRU1000 SoCs. >> >> Signed-off-by: Melody Olvera >> --- >> .../bindings/clock/qcom,gcc-qdru1000.yaml | 74 ++++++++ >> include/dt-bindings/clock/qcom,gcc-qdru1000.h | 170 ++++++++++++++++++ >> 2 files changed, 244 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml >> create mode 100644 include/dt-bindings/clock/qcom,gcc-qdru1000.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml >> new file mode 100644 >> index 000000000000..d92f558d547c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml >> @@ -0,0 +1,74 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdru.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Global Clock & Reset Controller Binding for QDU1000 and QRU1000 > Drop "Binding" Will do in v2. > >> + >> +maintainers: >> + - Melody Olvera >> + >> +description: | >> + Qualcomm global clock control module which supports the clocks, resets and >> + power domains on QDU1000 and QRU1000 >> + >> + See also: >> + - dt-bindings/clock/qcom,gcc-qdru1000.h > Full path Understood. > >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,gcc-qdu1000 >> + - qcom,gcc-qru1000 >> + >> + clocks: >> + items: >> + - description: Board XO source >> + - description: Sleep clock source >> + - description: PCIE 0 Pipe clock source (Optional clock) > Skip "Optional clock" > >> + - description: PCIE 0 Phy Auxiliary clock source (Optional clock) >> + - description: USB3 Phy wrapper pipe clock source (Optional clock) >> + minItems: 2 >> + >> + clock-names: >> + items: >> + - const: bi_tcxo >> + - const: sleep_clk >> + - const: pcie_0_pipe_clk # Optional clock > Skip "Optional clock" Will remove all optional clock instances. > >> + - const: pcie_0_phy_aux_clk # Optional clock >> + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock >> + minItems: 2 >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#reset-cells': >> + const: 1 >> + >> + reg: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - '#reset-cells' >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + clock-controller@100000 { >> + compatible = "qcom,gcc-qdu1000"; >> + reg = <0x00100000 0x001f4200>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >> + clock-names = "bi_tcxo", "sleep_clk"; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> +... >> diff --git a/include/dt-bindings/clock/qcom,gcc-qdru1000.h b/include/dt-bindings/clock/qcom,gcc-qdru1000.h >> new file mode 100644 >> index 000000000000..cdc5d1a6a007 >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,gcc-qdru1000.h >> @@ -0,0 +1,170 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ > Dual license. Good catch; will remove. > > > Best regards, > Krzysztof Thanks, Melody