From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 636F5C31E5E for ; Tue, 18 Jun 2019 09:26:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4278B2133F for ; Tue, 18 Jun 2019 09:26:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729274AbfFRJ0f (ORCPT ); Tue, 18 Jun 2019 05:26:35 -0400 Received: from foss.arm.com ([217.140.110.172]:59236 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729233AbfFRJ0f (ORCPT ); Tue, 18 Jun 2019 05:26:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 616ED344; Tue, 18 Jun 2019 02:26:34 -0700 (PDT) Received: from [10.1.197.61] (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2D6923F246; Tue, 18 Jun 2019 02:26:27 -0700 (PDT) Subject: Re: [PATCH V3 12/17] soc/tegra: pmc: allow support for more tegra wake To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> <1560843991-24123-13-git-send-email-skomatineni@nvidia.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1560843991-24123-13-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 18/06/2019 08:46, Sowjanya Komatineni wrote: > This patch allows to create separate irq_set_wake and irq_set_type > implementations for different tegra designs PMC that has different > wake models which require difference wake registers and different > programming sequence. > > AOWAKE model support is available for Tegra186 and Tegra194 only > and it resides within PMC and supports tiered wake architecture. > > Tegra210 and prior tegra designs uses PMC directly to receive wake > events and coordinate the wake sequence. > > Signed-off-by: Sowjanya Komatineni > --- > drivers/soc/tegra/pmc.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index edd4fe06810f..e87f29a35fcf 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -226,6 +226,8 @@ struct tegra_pmc_soc { > void (*setup_irq_polarity)(struct tegra_pmc *pmc, > struct device_node *np, > bool invert); > + int (*irq_set_wake)(struct irq_data *data, unsigned int on); > + int (*irq_set_type)(struct irq_data *data, unsigned int type); > > const char * const *reset_sources; > unsigned int num_reset_sources; > @@ -1919,7 +1921,7 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { > .alloc = tegra_pmc_irq_alloc, > }; > > -static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) > +static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) > { > struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); > unsigned int offset, bit; > @@ -1951,7 +1953,7 @@ static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) > return 0; > } > > -static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) > +static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) > { > struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); > u32 value; > @@ -2005,8 +2007,10 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc) > pmc->irq.irq_unmask = irq_chip_unmask_parent; > pmc->irq.irq_eoi = irq_chip_eoi_parent; > pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; > - pmc->irq.irq_set_type = tegra_pmc_irq_set_type; > - pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; > + if (pmc->soc->irq_set_type) > + pmc->irq.irq_set_type = pmc->soc->irq_set_type; > + if (pmc->soc->irq_set_wake) > + pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; Two cases: either the value is non NULL, and we assign it, or it is NULL, and we leave it to what it was, presumably NULL. I guess you can drop the both ifs. > > pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, > &tegra_pmc_irq_domain_ops, pmc); > @@ -2679,6 +2683,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { > .regs = &tegra186_pmc_regs, > .init = NULL, > .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, > + .irq_set_wake = tegra186_pmc_irq_set_wake, > + .irq_set_type = tegra186_pmc_irq_set_type, > .reset_sources = tegra186_reset_sources, > .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), > .reset_levels = tegra186_reset_levels, > Thanks, M. -- Jazz is not dead. It just smells funny...