From: Jon Hunter <jonathanh@nvidia.com>
To: Joseph Lo <josephl@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH V2 08/21] clk: tegra: dfll: round down voltages based on alignment
Date: Thu, 13 Dec 2018 11:46:27 +0000 [thread overview]
Message-ID: <c1ce50e0-fccf-aa37-361c-4dd9367b092d@nvidia.com> (raw)
In-Reply-To: <20181213093438.29621-9-josephl@nvidia.com>
On 13/12/2018 09:34, Joseph Lo wrote:
> When generating the OPP table, the voltages are round down with the
> alignment from the regulator. The alignment should be applied for
> voltages look up as well.
>
> Based on the work of Penny Chiu <pchiu@nvidia.com>.
>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> *V2:
> - s/align_volt/align_step/
> - s/reg_volt/reg_volt_id/
> ---
> drivers/clk/tegra/clk-dfll.c | 26 +++++++++++++++-----------
> 1 file changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
> index 72e02898006c..b3668073d9b4 100644
> --- a/drivers/clk/tegra/clk-dfll.c
> +++ b/drivers/clk/tegra/clk-dfll.c
> @@ -804,17 +804,17 @@ static void dfll_init_out_if(struct tegra_dfll *td)
> static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
> {
> struct dev_pm_opp *opp;
> - int i, uv;
> + int i, align_step;
>
> opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
> if (IS_ERR(opp))
> return PTR_ERR(opp);
>
> - uv = dev_pm_opp_get_voltage(opp);
> + align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
> dev_pm_opp_put(opp);
>
> for (i = td->lut_bottom; i < td->lut_size; i++) {
> - if (td->lut_uv[i] >= uv)
> + if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)
> return i;
> }
>
> @@ -1532,15 +1532,17 @@ static int dfll_init(struct tegra_dfll *td)
> */
> static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
> {
> - int i, n_voltages, reg_uV;
> + int i, n_voltages, reg_volt_id, align_step;
>
> + align_step = uV / td->soc->alignment.step_uv;
> n_voltages = regulator_count_voltages(td->vdd_reg);
> for (i = 0; i < n_voltages; i++) {
> - reg_uV = regulator_list_voltage(td->vdd_reg, i);
> - if (reg_uV < 0)
> + reg_volt_id = regulator_list_voltage(td->vdd_reg, i) /
> + td->soc->alignment.step_uv;
> + if (reg_volt_id < 0)
I don't think that this will work. If the step is say 10000 and we
return an error code greater than -10000, we will end up with 0.
> break;
>
> - if (uV == reg_uV)
> + if (align_step == reg_volt_id)
> return i;
> }
>
> @@ -1554,15 +1556,17 @@ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
> * */
> static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
> {
> - int i, n_voltages, reg_uV;
> + int i, n_voltages, reg_volt_id, align_step;
>
> + align_step = uV / td->soc->alignment.step_uv;
> n_voltages = regulator_count_voltages(td->vdd_reg);
> for (i = 0; i < n_voltages; i++) {
> - reg_uV = regulator_list_voltage(td->vdd_reg, i);
> - if (reg_uV < 0)
> + reg_volt_id = regulator_list_voltage(td->vdd_reg, i) /
> + td->soc->alignment.step_uv;
> + if (reg_volt_id < 0)
Same here.
> break;
>
> - if (uV <= reg_uV)
> + if (align_step <= reg_volt_id)
> return i;
> }
>
>
--
nvpublic
next prev parent reply other threads:[~2018-12-13 11:46 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-13 9:34 [PATCH V2 00/21] Tegra210 DFLL support Joseph Lo
2018-12-13 9:34 ` [PATCH V2 01/21] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-13 9:34 ` [PATCH V2 02/21] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-13 9:34 ` [PATCH V2 03/21] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-13 9:34 ` [PATCH V2 04/21] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-13 9:34 ` [PATCH V2 05/21] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-13 9:34 ` [PATCH V2 06/21] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-13 11:18 ` Jon Hunter
2018-12-14 7:08 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 07/21] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-13 11:41 ` Jon Hunter
2018-12-14 7:11 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 08/21] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-13 11:46 ` Jon Hunter [this message]
2018-12-14 7:18 ` Joseph Lo
2018-12-14 10:00 ` Jon Hunter
2018-12-13 9:34 ` [PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs Joseph Lo
2018-12-13 12:46 ` Jon Hunter
2018-12-14 7:42 ` Joseph Lo
2018-12-17 11:38 ` Peter De Schrijver
2018-12-13 9:34 ` [PATCH V2 10/21] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-13 12:50 ` Jon Hunter
2018-12-14 7:43 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 11/21] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-13 9:34 ` [PATCH V2 12/21] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-13 10:49 ` Rafael J. Wysocki
2018-12-13 12:55 ` Jon Hunter
2018-12-18 5:34 ` Viresh Kumar
2018-12-13 9:34 ` [PATCH V2 13/21] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-13 9:34 ` [PATCH V2 14/21] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2018-12-13 13:09 ` Jon Hunter
2018-12-18 5:33 ` Viresh Kumar
2018-12-13 9:34 ` [PATCH V2 15/21] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-13 9:34 ` [PATCH V2 16/21] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-13 9:34 ` [PATCH V2 17/21] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-13 9:34 ` [PATCH V2 18/21] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-13 13:11 ` Jon Hunter
2018-12-13 9:34 ` [PATCH V2 19/21] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-13 9:34 ` [PATCH V2 20/21] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-13 9:34 ` [PATCH V2 21/21] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
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