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Subject: Re: [PATCH v3 06/15] clk: tegra: Remove tegra_pmc_clk_init along with
 clk ids
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
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From:   Sowjanya Komatineni <skomatineni@nvidia.com>
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On 12/7/19 7:04 AM, Dmitry Osipenko wrote:
> 07.12.2019 17:43, Dmitry Osipenko =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>> 07.12.2019 17:33, Dmitry Osipenko =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>>> 06.12.2019 05:48, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>>>> Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,
>>>> clk_out_3 and blink output in tegra_pmc_init() which does direct Tegra
>>>> PMC access during clk_ops and these PMC register read and write access
>>>> will not happen when PMC is in secure mode.
>>>>
>>>> Any direct PMC register access from non-secure world will not go
>>>> through and all the PMC clocks and blink control are done in Tegra PMC
>>>> driver with PMC as clock provider.
>>>>
>>>> This patch removes tegra_pmc_clk_init along with corresponding clk ids
>>>> from Tegra clock driver.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>> [snip]
>>>
>>>> @@ -1230,9 +1222,6 @@ static struct tegra_clk_init_table init_table[] =
__initdata =3D {
>>>>   	{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
>>>>   	{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
>>>>   	{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
>>> Perhaps these clocks do not need to be always-enabled?
>>>
>>> [snip]
>>>
>> Also, EXTERN1 parent configuration should be moved to the audio
>> driver/device-tree as well.
> Ah, I missed that it's done in the patch #10.
Yes its done in Patch#10
>
>> Maybe it even makes sense to move the whole configuration, including
>> PLLA. I don't see why clk driver need to do something for the audio driv=
er.

Current ASoC driver already takes care of PLLA rate and enables.

So PLLA init can be removed from clock driver too. I didn't went through=20
complete audio driver to be confident to remove this.

But PLLA is needed for i2s clock also and currently I2S driver takes=20
care of only I2S clock rate using PLLA as parent set by clock driver and=20
clock driver enables PLLA earlier to have it ready by the time both I2S=20
driver and ASoC driver .