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* [PATCH v3 00/16] Initial support for Marvell MMP3 SoC
@ 2019-08-30 22:07 Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 01/16] dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method Lubomir Rintel
                   ` (16 more replies)
  0 siblings, 17 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk

Hi, 

this is the third spin of a patch set that adds support for the Marvell
MMP3 processor, that I'd eventually love to see land in the Arm SoC
tree. MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet
and Dell Wyse 3020/Tx0D thin clients. 

Compared to v2, there's a handful of fixes in response to reviews. Four
irqchip patches have been removed because they've been applied to the
irqchip-next tree. Details in individual patches.
 
Thank you
Lubo



^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 01/16] dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 02/16] dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema Lubomir Rintel
                   ` (15 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel, Rob Herring

Add the enable method for the second PJ4B core of the Marvell MMP3 SoC.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>

---
Changes since v1:
- Add Rob's Reviewed-by tag

 Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index aa40b074b8648..fcba84e32e68a 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -186,6 +186,7 @@ properties:
               - marvell,armada-390-smp
               - marvell,armada-xp-smp
               - marvell,98dx3236-smp
+              - marvell,mmp3-smp
               - mediatek,mt6589-smp
               - mediatek,mt81xx-tz-smp
               - qcom,gcc-msm8660
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 02/16] dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 01/16] dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-09-02 13:39   ` Rob Herring
  2019-08-30 22:07 ` [PATCH v3 03/16] dt-bindings: arm: mrvl: Document MMP3 compatible string Lubomir Rintel
                   ` (14 subsequent siblings)
  16 siblings, 1 reply; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

Convert Marvell MMP SoC bindings to DT schema format using json-schema.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

---
Changes since v2:
- Add mrvl,pxa910
- s/MMP2 Brownstone Board/MMP2 based boards/

Changes since v1:
- Added this patch

 .../devicetree/bindings/arm/mrvl/mrvl.txt     | 14 --------
 .../devicetree/bindings/arm/mrvl/mrvl.yaml    | 32 +++++++++++++++++++
 2 files changed, 32 insertions(+), 14 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml

diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
deleted file mode 100644
index 951687528efb0..0000000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Marvell Platforms Device Tree Bindings
-----------------------------------------------------
-
-PXA168 Aspenite Board
-Required root node properties:
-	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
-
-PXA910 DKB Board
-Required root node properties:
-	- compatible = "mrvl,pxa910-dkb";
-
-MMP2 Brownstone Board
-Required root node properties:
-	- compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
new file mode 100644
index 0000000000000..ef59d6e35bb66
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Platforms Device Tree Bindings
+
+maintainers:
+  - Lubomir Rintel <lkundrak@v3.sk>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: PXA168 Aspenite Board
+        items:
+          - enum:
+              - mrvl,pxa168-aspenite
+          - const: mrvl,pxa168
+      - description: PXA910 DKB Board
+        items:
+          - enum:
+              - mrvl,pxa910-dkb
+          - const: mrvl,pxa910
+      - description: MMP2 based boards
+        items:
+          - enum:
+              - mrvl,mmp2-brownstone
+          - const: mrvl,mmp2
+...
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 03/16] dt-bindings: arm: mrvl: Document MMP3 compatible string
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 01/16] dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 02/16] dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 04/16] dt-bindings: mrvl,intc: Add a MMP3 interrupt controller Lubomir Rintel
                   ` (13 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel, Rob Herring

Marvel MMP3 is a successor to MMP2, containing similar peripherals with two
PJ4B cores.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>

---
Changes since v2:
- s/MMP3 SoC/MMP3 based boards/, for consistency with MMP2
- Rob's review

Changes since v1:
- Rebased on top of mrvl.txt->mrvl.yaml conversion

 Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
index ef59d6e35bb66..818dfe6de5120 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -29,4 +29,7 @@ properties:
           - enum:
               - mrvl,mmp2-brownstone
           - const: mrvl,mmp2
+      - description: MMP3 based boards
+        items:
+          - const: mrvl,mmp3
 ...
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 04/16] dt-bindings: mrvl,intc: Add a MMP3 interrupt controller
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (2 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 03/16] dt-bindings: arm: mrvl: Document MMP3 compatible string Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 05/16] dt-bindings: phy-mmp3-usb: Add bindings Lubomir Rintel
                   ` (12 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel, Rob Herring

Similar to MMP2 one, but has an extra range for the other core. The
muxes stay the same.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>

---
Changes since v2:
- Add Rob's Reviewed-by tag

Changes since v1:
- Reformat the compatible property documentation to higlight the valid
  combinations
- Drop an unneeded mmp3-intc example

 .../bindings/interrupt-controller/mrvl,intc.txt    | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
index 608fee15a4cfc..a0ed02725a9d7 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
@@ -1,13 +1,17 @@
 * Marvell MMP Interrupt controller
 
 Required properties:
-- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
-  "mrvl,mmp2-mux-intc"
+- compatible : Should be
+               "mrvl,mmp-intc" on Marvel MMP,
+               "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
+               "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
 - reg : Address and length of the register set of the interrupt controller.
   If the interrupt controller is intc, address and length means the range
-  of the whole interrupt controller. If the interrupt controller is mux-intc,
-  address and length means one register. Since address of mux-intc is in the
-  range of intc. mux-intc is secondary interrupt controller.
+  of the whole interrupt controller. The "marvell,mmp3-intc" controller
+  also has a secondary range for the second CPU core.  If the interrupt
+  controller is mux-intc, address and length means one register. Since
+  address of mux-intc is in the range of intc. mux-intc is secondary
+  interrupt controller.
 - reg-names : Name of the register set of the interrupt controller. It's
   only required in mux-intc interrupt controller.
 - interrupts : Should be the port interrupt shared by mux interrupts. It's
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 05/16] dt-bindings: phy-mmp3-usb: Add bindings
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (3 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 04/16] dt-bindings: mrvl,intc: Add a MMP3 interrupt controller Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 06/16] ARM: l2c: add definition for FWA in PL310 aux register Lubomir Rintel
                   ` (11 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel, Rob Herring

This is the PHY chip for USB OTG on MMP3 platform.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>

---
Changes since v2:
- Add Rob's Reviewed-by tag

Changes since v1:
- s/usbphy@/usb-phy@/
- Dropped a reference to Documentation/phy.txt

 .../devicetree/bindings/phy/phy-mmp3-usb.txt        | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
new file mode 100644
index 0000000000000..7183b9102f917
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
@@ -0,0 +1,13 @@
+Marvell MMP3 USB PHY
+--------------------
+
+Required properties:
+- compatible: must be "marvell,mmp3-usb-phy"
+- #phy-cells: must be 0
+
+Example:
+	usb-phy: usb-phy@d4207000 {
+		compatible = "marvell,mmp3-usb-phy";
+		reg = <0xd4207000 0x40>;
+		#phy-cells = <0>;
+	};
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 06/16] ARM: l2c: add definition for FWA in PL310 aux register
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (4 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 05/16] dt-bindings: phy-mmp3-usb: Add bindings Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 07/16] ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP Lubomir Rintel
                   ` (10 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

The PL310 also has a "Force write allocate" bits in the Auxiliary
Control Register.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 arch/arm/include/asm/hardware/cache-l2x0.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 32edfadb15935..a6d4ee86ba543 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -118,6 +118,8 @@
 #define L310_AUX_CTRL_STORE_LIMITATION		BIT(11)	/* R2P0+ */
 #define L310_AUX_CTRL_EXCLUSIVE_CACHE		BIT(12)
 #define L310_AUX_CTRL_ASSOCIATIVITY_16		BIT(16)
+#define L310_AUX_CTRL_FWA_SHIFT			23
+#define L310_AUX_CTRL_FWA_MASK			(3 << 23)
 #define L310_AUX_CTRL_CACHE_REPLACE_RR		BIT(25)	/* R2P0+ */
 #define L310_AUX_CTRL_NS_LOCKDOWN		BIT(26)
 #define L310_AUX_CTRL_NS_INT_CTRL		BIT(27)
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 07/16] ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (5 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 06/16] ARM: l2c: add definition for FWA in PL310 aux register Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 08/16] ARM: mmp: map the PGU as well Lubomir Rintel
                   ` (9 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

MMP3 has a PJ4B with a Tauros 3 cache controller that uses CACHE_L2X0
instead, while CACHE_TAUROS2 is present on PJ4 and PJ1 (Mohawk) based
platforms only.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 arch/arm/mm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c1222c0e9fd3b..5255aa64618b5 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1041,7 +1041,7 @@ endif
 
 config CACHE_TAUROS2
 	bool "Enable the Tauros2 L2 cache controller"
-	depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
+	depends on (CPU_MOHAWK || CPU_PJ4)
 	default y
 	select OUTER_CACHE
 	help
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 08/16] ARM: mmp: map the PGU as well
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (6 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 07/16] ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 09/16] ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE Lubomir Rintel
                   ` (8 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

The MMP2 and later includes a system control unit in this area. We'll need
that to initialize the secondary core on MMP3.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 arch/arm/mach-mmp/addr-map.h |  7 +++++++
 arch/arm/mach-mmp/common.c   | 15 +++++++++++++++
 arch/arm/mach-mmp/common.h   |  1 +
 arch/arm/mach-mmp/mmp2-dt.c  |  2 +-
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mmp/addr-map.h b/arch/arm/mach-mmp/addr-map.h
index 25edf6a92276e..3dc2f0b0ecba5 100644
--- a/arch/arm/mach-mmp/addr-map.h
+++ b/arch/arm/mach-mmp/addr-map.h
@@ -20,6 +20,10 @@
 #define AXI_VIRT_BASE		IOMEM(0xfe200000)
 #define AXI_PHYS_SIZE		0x00200000
 
+#define PGU_PHYS_BASE		0xe0000000
+#define PGU_VIRT_BASE		IOMEM(0xfe400000)
+#define PGU_PHYS_SIZE		0x00100000
+
 /* Static Memory Controller - Chip Select 0 and 1 */
 #define SMC_CS0_PHYS_BASE	0x80000000
 #define SMC_CS0_PHYS_SIZE	0x10000000
@@ -38,4 +42,7 @@
 #define CIU_VIRT_BASE		(AXI_VIRT_BASE + 0x82c00)
 #define CIU_REG(x)		(CIU_VIRT_BASE + (x))
 
+#define SCU_VIRT_BASE		(PGU_VIRT_BASE)
+#define SCU_REG(x)		(SCU_VIRT_BASE + (x))
+
 #endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 6684abc7708bd..2ee08c78e8bc9 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -36,6 +36,15 @@ static struct map_desc standard_io_desc[] __initdata = {
 	},
 };
 
+static struct map_desc mmp2_io_desc[] __initdata = {
+	{
+		.pfn		= __phys_to_pfn(PGU_PHYS_BASE),
+		.virtual	= (unsigned long)PGU_VIRT_BASE,
+		.length		= PGU_PHYS_SIZE,
+		.type		= MT_DEVICE,
+	},
+};
+
 void __init mmp_map_io(void)
 {
 	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
@@ -44,6 +53,12 @@ void __init mmp_map_io(void)
 	mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
 
+void __init mmp2_map_io(void)
+{
+	mmp_map_io();
+	iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc));
+}
+
 void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
 	soft_restart(0);
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 483b8b6d3005a..ed56b3f15b45e 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -5,4 +5,5 @@
 extern void mmp_timer_init(int irq, unsigned long rate);
 
 extern void __init mmp_map_io(void);
+extern void __init mmp2_map_io(void);
 extern void mmp_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 305a9daba6d68..8eec881191f4b 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -33,7 +33,7 @@ static const char *const mmp2_dt_board_compat[] __initconst = {
 };
 
 DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
-	.map_io		= mmp_map_io,
+	.map_io		= mmp2_map_io,
 	.init_time	= mmp_init_time,
 	.dt_compat	= mmp2_dt_board_compat,
 MACHINE_END
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 09/16] ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (7 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 08/16] ARM: mmp: map the PGU as well Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 10/16] ARM: mmp: define MMP_CHIPID by the means of CIU_REG() Lubomir Rintel
                   ` (7 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

This makes things just a tiny bit simpler.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 arch/arm/mach-mmp/mmp-dt.c  |  5 ++---
 arch/arm/mach-mmp/mmp2-dt.c |  5 ++---
 arch/arm/mach-mmp/time.c    | 38 +++++++++++--------------------------
 3 files changed, 15 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 35559792d5cca..91214996acecc 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -9,14 +9,13 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
+#include <linux/clocksource.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
-extern void __init mmp_dt_init_timer(void);
-
 static const char *const pxa168_dt_board_compat[] __initconst = {
 	"mrvl,pxa168-aspenite",
 	NULL,
@@ -32,8 +31,8 @@ static void __init mmp_init_time(void)
 #ifdef CONFIG_CACHE_TAUROS2
 	tauros2_init(0);
 #endif
-	mmp_dt_init_timer();
 	of_clk_init(NULL);
+	timer_probe();
 }
 
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 8eec881191f4b..510c762ddc484 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -10,21 +10,20 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
+#include <linux/clocksource.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
-extern void __init mmp_dt_init_timer(void);
-
 static void __init mmp_init_time(void)
 {
 #ifdef CONFIG_CACHE_TAUROS2
 	tauros2_init(0);
 #endif
 	of_clk_init(NULL);
-	mmp_dt_init_timer();
+	timer_probe();
 }
 
 static const char *const mmp2_dt_board_compat[] __initconst = {
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 483df32583be6..3f6fd0be00512 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -195,30 +195,17 @@ void __init mmp_timer_init(int irq, unsigned long rate)
 	clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
 }
 
-#ifdef CONFIG_OF
-static const struct of_device_id mmp_timer_dt_ids[] = {
-	{ .compatible = "mrvl,mmp-timer", },
-	{}
-};
-
-void __init mmp_dt_init_timer(void)
+static int __init mmp_dt_init_timer(struct device_node *np)
 {
-	struct device_node *np;
 	struct clk *clk;
 	int irq, ret;
 	unsigned long rate;
 
-	np = of_find_matching_node(NULL, mmp_timer_dt_ids);
-	if (!np) {
-		ret = -ENODEV;
-		goto out;
-	}
-
 	clk = of_clk_get(np, 0);
 	if (!IS_ERR(clk)) {
 		ret = clk_prepare_enable(clk);
 		if (ret)
-			goto out;
+			return ret;
 		rate = clk_get_rate(clk) / 2;
 	} else if (cpu_is_pj4()) {
 		rate = 6500000;
@@ -227,18 +214,15 @@ void __init mmp_dt_init_timer(void)
 	}
 
 	irq = irq_of_parse_and_map(np, 0);
-	if (!irq) {
-		ret = -EINVAL;
-		goto out;
-	}
+	if (!irq)
+		return -EINVAL;
+
 	mmp_timer_base = of_iomap(np, 0);
-	if (!mmp_timer_base) {
-		ret = -ENOMEM;
-		goto out;
-	}
+	if (!mmp_timer_base)
+		return -ENOMEM;
+
 	mmp_timer_init(irq, rate);
-	return;
-out:
-	pr_err("Failed to get timer from device tree with error:%d\n", ret);
+	return 0;
 }
-#endif
+
+TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 10/16] ARM: mmp: define MMP_CHIPID by the means of CIU_REG()
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (8 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 09/16] ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 11/16] ARM: mmp: add support for MMP3 SoC Lubomir Rintel
                   ` (6 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

A rather trivial cosmetic improvement.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 arch/arm/mach-mmp/common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 2ee08c78e8bc9..24c689a01ecb7 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -17,7 +17,7 @@
 
 #include "common.h"
 
-#define MMP_CHIPID	(AXI_VIRT_BASE + 0x82c00)
+#define MMP_CHIPID	CIU_REG(0x00)
 
 unsigned int mmp_chip_id;
 EXPORT_SYMBOL(mmp_chip_id);
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 11/16] ARM: mmp: add support for MMP3 SoC
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (9 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 10/16] ARM: mmp: define MMP_CHIPID by the means of CIU_REG() Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-09-06 23:48   ` Stephen Boyd
  2019-08-30 22:07 ` [PATCH v3 12/16] ARM: mmp: add SMP support Lubomir Rintel
                   ` (5 subsequent siblings)
  16 siblings, 1 reply; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

Similar to MMP2, which this patch is based on. Known differencies from MMP2
are:

* Two PJ4B cores instead of one PJ4
* Tauros 3 L2 cache controller instead of Tauros 2
* A GIC interrupt controller optionally used instead of the MMP one
* A TWD local timer
* Different USB2 PHY
* A USB3 SS controller
* More interrupt muxes

Hard to tell what else is different, because documentation is not
available.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

---
Changes since v1:
- Add CONFIG_COMMON_CLK_MMP2 to streamline the Makefile rule a tiny bit.

 arch/arm/mach-mmp/Kconfig   | 22 ++++++++++++++++++++--
 arch/arm/mach-mmp/Makefile  |  1 +
 arch/arm/mach-mmp/cputype.h | 27 +++++++++++++++++++++++++++
 arch/arm/mach-mmp/mmp3.c    | 29 +++++++++++++++++++++++++++++
 arch/arm/mach-mmp/time.c    |  3 ++-
 drivers/clk/Kconfig         |  5 +++++
 drivers/clk/mmp/Makefile    |  2 +-
 7 files changed, 85 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-mmp/mmp3.c

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 0440109e973b9..b58a03b18bdef 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -1,13 +1,13 @@
 # SPDX-License-Identifier: GPL-2.0-only
 menuconfig ARCH_MMP
-	bool "Marvell PXA168/910/MMP2"
+	bool "Marvell PXA168/910/MMP2/MMP3"
 	depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
 	select GPIO_PXA
 	select GPIOLIB
 	select PINCTRL
 	select PLAT_PXA
 	help
-	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
+	  Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines.
 
 if ARCH_MMP
 
@@ -129,6 +129,24 @@ config MACH_MMP2_DT
 	  Include support for Marvell MMP2 based platforms using
 	  the device tree.
 
+config MACH_MMP3_DT
+	bool "Support MMP3 (ARMv7) platforms"
+	depends on ARCH_MULTI_V7
+	select ARM_GIC
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select CACHE_L2X0
+	select PINCTRL
+	select PINCTRL_SINGLE
+	select ARCH_HAS_RESET_CONTROLLER
+	select CPU_PJ4B
+	select PM_GENERIC_DOMAINS if PM
+	select PM_GENERIC_DOMAINS_OF if PM && OF
+	help
+	  Say 'Y' here if you want to include support for platforms
+	  with Marvell MMP3 processor, also known as PXA2128 or
+	  Armada 620.
+
 endmenu
 
 config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 8f267c7bc6e86..322c1c97dc900 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -34,5 +34,6 @@ obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o
 obj-$(CONFIG_MACH_MMP2_DT)	+= mmp2-dt.o
+obj-$(CONFIG_MACH_MMP3_DT)	+= mmp3.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/cputype.h b/arch/arm/mach-mmp/cputype.h
index a96abcf521b4b..c3ec88983e940 100644
--- a/arch/arm/mach-mmp/cputype.h
+++ b/arch/arm/mach-mmp/cputype.h
@@ -18,6 +18,8 @@
  * MMP2	     Z0	   0x560f5811   0x00F00410
  * MMP2      Z1    0x560f5811   0x00E00410
  * MMP2      A0    0x560f5811   0x00A0A610
+ * MMP3      A0    0x562f5842   0x00A02128
+ * MMP3      B0    0x562f5842   0x00B02128
  */
 
 extern unsigned int mmp_chip_id;
@@ -55,4 +57,29 @@ static inline int cpu_is_mmp2(void)
 #define cpu_is_mmp2()	(0)
 #endif
 
+#ifdef CONFIG_MACH_MMP3_DT
+static inline int cpu_is_mmp3(void)
+{
+	return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
+		((mmp_chip_id & 0xffff) == 0x2128);
+}
+
+static inline int cpu_is_mmp3_a0(void)
+{
+	return (cpu_is_mmp3() &&
+		((mmp_chip_id & 0x00ff0000) == 0x00a00000));
+}
+
+static inline int cpu_is_mmp3_b0(void)
+{
+	return (cpu_is_mmp3() &&
+		((mmp_chip_id & 0x00ff0000) == 0x00b00000));
+}
+
+#else
+#define cpu_is_mmp3()		(0)
+#define cpu_is_mmp3_a0()	(0)
+#define cpu_is_mmp3_b0()	(0)
+#endif
+
 #endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/mmp3.c b/arch/arm/mach-mmp/mmp3.c
new file mode 100644
index 0000000000000..b0e86964f302a
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp3.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *  Marvell MMP3 aka PXA2128 aka 88AP2128 support
+ *
+ *  Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include "common.h"
+
+static const char *const mmp3_dt_board_compat[] __initconst = {
+	"marvell,mmp3",
+	NULL,
+};
+
+DT_MACHINE_START(MMP2_DT, "Marvell MMP3")
+	.map_io		= mmp2_map_io,
+	.dt_compat	= mmp3_dt_board_compat,
+	.l2c_aux_val	= 1 << L310_AUX_CTRL_FWA_SHIFT |
+			  L310_AUX_CTRL_DATA_PREFETCH |
+			  L310_AUX_CTRL_INSTR_PREFETCH,
+	.l2c_aux_mask	= 0xc20fffff,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 3f6fd0be00512..8f4cacbf640e9 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -155,7 +155,8 @@ static void __init timer_config(void)
 
 	__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
 
-	ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
+	ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
+		(TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
 		(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
 	__raw_writel(ccr, mmp_timer_base + TMR_CCR);
 
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 801fa1cd03217..8bb2ac83a1fcc 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -301,6 +301,11 @@ config COMMON_CLK_STM32H7
 	---help---
 	  Support for stm32h7 SoC family clocks
 
+config COMMON_CLK_MMP2
+	def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
+	help
+	  Support for Marvell MMP2 and MMP3 SoC clocks
+
 config COMMON_CLK_BD718XX
 	tristate "Clock driver for ROHM BD718x7 PMIC"
 	depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 7bc7ac69391e3..acc141adf087c 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -8,7 +8,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
 
 obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
-obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
+obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 12/16] ARM: mmp: add SMP support
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (10 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 11/16] ARM: mmp: add support for MMP3 SoC Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 13/16] ARM: mmp: move cputype.h to include/linux/soc/ Lubomir Rintel
                   ` (4 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

Used to bring up the second core on MMP3.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

---
Changes since v2:
- Wrap secondary_startup with __pa_symbol(), instead of
  SW_BRANCH_VIRT_ADDR.

Changes since v1:
- Wrap SW_BRANCH_VIRT_ADDR with __pa_symbol()

 arch/arm/mach-mmp/Makefile  |  3 +++
 arch/arm/mach-mmp/platsmp.c | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 arch/arm/mach-mmp/platsmp.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 322c1c97dc900..7b3a7f979eece 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -22,6 +22,9 @@ ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)	+= pm-pxa910.o
 obj-$(CONFIG_CPU_MMP2)		+= pm-mmp2.o
 endif
+ifeq ($(CONFIG_SMP),y)
+obj-$(CONFIG_MACH_MMP3_DT)	+= platsmp.o
+endif
 
 # board support
 obj-$(CONFIG_MACH_ASPENITE)	+= aspenite.o
diff --git a/arch/arm/mach-mmp/platsmp.c b/arch/arm/mach-mmp/platsmp.c
new file mode 100644
index 0000000000000..c99405469bb4b
--- /dev/null
+++ b/arch/arm/mach-mmp/platsmp.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+#include <linux/io.h>
+#include <asm/smp_scu.h>
+#include <asm/smp.h>
+#include "addr-map.h"
+
+#define SW_BRANCH_VIRT_ADDR	CIU_REG(0x24)
+
+static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	/*
+	 * Apparently, the boot ROM on the second core spins on this
+	 * register becoming non-zero and then jumps to the address written
+	 * there. No IPIs involved.
+	 */
+	__raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
+	return 0;
+}
+
+static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
+{
+	scu_enable(SCU_VIRT_BASE);
+}
+
+static const struct smp_operations mmp3_smp_ops __initconst = {
+	.smp_prepare_cpus	= mmp3_smp_prepare_cpus,
+	.smp_boot_secondary	= mmp3_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 13/16] ARM: mmp: move cputype.h to include/linux/soc/
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (11 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 12/16] ARM: mmp: add SMP support Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-09-02  8:15   ` kbuild test robot
  2019-08-30 22:07 ` [PATCH v3 14/16] ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h Lubomir Rintel
                   ` (3 subsequent siblings)
  16 siblings, 1 reply; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

Let's move cputype.h away from mach-mmp/ so that the drivers outside that
directory are able to tell the precise silicon revision. The MMP3 USB OTG
PHY driver needs this.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 MAINTAINERS                                            | 1 +
 arch/arm/mach-mmp/common.c                             | 2 +-
 arch/arm/mach-mmp/devices.c                            | 2 +-
 arch/arm/mach-mmp/mmp2.c                               | 2 +-
 arch/arm/mach-mmp/pm-mmp2.c                            | 2 +-
 arch/arm/mach-mmp/pm-pxa910.c                          | 2 +-
 arch/arm/mach-mmp/pxa168.c                             | 2 +-
 arch/arm/mach-mmp/pxa910.c                             | 2 +-
 arch/arm/mach-mmp/time.c                               | 2 +-
 {arch/arm/mach-mmp => include/linux/soc/mmp}/cputype.h | 0
 10 files changed, 9 insertions(+), 8 deletions(-)
 rename {arch/arm/mach-mmp => include/linux/soc/mmp}/cputype.h (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9cbcf167bdd08..176ef19f0b9db 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10797,6 +10797,7 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Odd Fixes
 F:	arch/arm/boot/dts/mmp*
 F:	arch/arm/mach-mmp/
+F:	linux/soc/mmp/
 
 MMU GATHER AND TLB INVALIDATION
 M:	Will Deacon <will@kernel.org>
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 24c689a01ecb7..e94349d4726ca 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -13,7 +13,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include "addr-map.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index 130c1a603ba29..18bee66a671ff 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -11,7 +11,7 @@
 #include <asm/irq.h>
 #include "irqs.h"
 #include "devices.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 #include "regs-usb.h"
 
 int __init pxa_register_device(struct pxa_device_desc *desc,
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 18ea3e1a26e69..bbc4c2274de3a 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,7 @@
 #include <asm/mach/time.h>
 #include "addr-map.h"
 #include "regs-apbc.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 #include "irqs.h"
 #include "mfp.h"
 #include "devices.h"
diff --git a/arch/arm/mach-mmp/pm-mmp2.c b/arch/arm/mach-mmp/pm-mmp2.c
index 2923dd5732a62..2d86381e152d6 100644
--- a/arch/arm/mach-mmp/pm-mmp2.c
+++ b/arch/arm/mach-mmp/pm-mmp2.c
@@ -17,7 +17,7 @@
 #include <linux/interrupt.h>
 #include <asm/mach-types.h>
 
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 #include "addr-map.h"
 #include "pm-mmp2.h"
 #include "regs-icu.h"
diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c
index 58535ce206dc5..69ebe18ff209f 100644
--- a/arch/arm/mach-mmp/pm-pxa910.c
+++ b/arch/arm/mach-mmp/pm-pxa910.c
@@ -18,7 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/outercache.h>
 
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 #include "addr-map.h"
 #include "pm-pxa910.h"
 #include "regs-icu.h"
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 6e02774889679..b642e900727a5 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -21,7 +21,7 @@
 #include "addr-map.h"
 #include "clock.h"
 #include "common.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 #include "devices.h"
 #include "irqs.h"
 #include "mfp.h"
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index cba31c758dea6..b19a069d9fabe 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -18,7 +18,7 @@
 #include <asm/mach/time.h>
 #include "addr-map.h"
 #include "regs-apbc.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 #include "irqs.h"
 #include "mfp.h"
 #include "devices.h"
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 8f4cacbf640e9..110dcb3314d13 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -33,7 +33,7 @@
 #include "regs-timers.h"
 #include "regs-apbc.h"
 #include "irqs.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
 #include "clock.h"
 
 #define TIMERS_VIRT_BASE	TIMERS1_VIRT_BASE
diff --git a/arch/arm/mach-mmp/cputype.h b/include/linux/soc/mmp/cputype.h
similarity index 100%
rename from arch/arm/mach-mmp/cputype.h
rename to include/linux/soc/mmp/cputype.h
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 14/16] ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (12 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 13/16] ARM: mmp: move cputype.h to include/linux/soc/ Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-08-30 22:07 ` [PATCH v3 15/16] phy: phy-mmp3-usb: add a new driver Lubomir Rintel
                   ` (2 subsequent siblings)
  16 siblings, 0 replies; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

Nothing in mach-mmp/ uses them and they belong to the PHY driver.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 arch/arm/mach-mmp/regs-usb.h | 94 ------------------------------------
 1 file changed, 94 deletions(-)

diff --git a/arch/arm/mach-mmp/regs-usb.h b/arch/arm/mach-mmp/regs-usb.h
index d9f08c1601542..ed0d1aa0ad6c9 100644
--- a/arch/arm/mach-mmp/regs-usb.h
+++ b/arch/arm/mach-mmp/regs-usb.h
@@ -121,100 +121,6 @@
 
 #define UTMI_OTG_ADDON_OTG_ON			(1 << 0)
 
-/* For MMP3 USB Phy */
-#define USB2_PLL_REG0		0x4
-#define USB2_PLL_REG1		0x8
-#define USB2_TX_REG0		0x10
-#define USB2_TX_REG1		0x14
-#define USB2_TX_REG2		0x18
-#define USB2_RX_REG0		0x20
-#define USB2_RX_REG1		0x24
-#define USB2_RX_REG2		0x28
-#define USB2_ANA_REG0		0x30
-#define USB2_ANA_REG1		0x34
-#define USB2_ANA_REG2		0x38
-#define USB2_DIG_REG0		0x3C
-#define USB2_DIG_REG1		0x40
-#define USB2_DIG_REG2		0x44
-#define USB2_DIG_REG3		0x48
-#define USB2_TEST_REG0		0x4C
-#define USB2_TEST_REG1		0x50
-#define USB2_TEST_REG2		0x54
-#define USB2_CHARGER_REG0	0x58
-#define USB2_OTG_REG0		0x5C
-#define USB2_PHY_MON0		0x60
-#define USB2_RESETVE_REG0	0x64
-#define USB2_ICID_REG0		0x78
-#define USB2_ICID_REG1		0x7C
-
-/* USB2_PLL_REG0 */
-/* This is for Ax stepping */
-#define USB2_PLL_FBDIV_SHIFT_MMP3		0
-#define USB2_PLL_FBDIV_MASK_MMP3		(0xFF << 0)
-
-#define USB2_PLL_REFDIV_SHIFT_MMP3		8
-#define USB2_PLL_REFDIV_MASK_MMP3		(0xF << 8)
-
-#define USB2_PLL_VDD12_SHIFT_MMP3		12
-#define USB2_PLL_VDD18_SHIFT_MMP3		14
-
-/* This is for B0 stepping */
-#define USB2_PLL_FBDIV_SHIFT_MMP3_B0		0
-#define USB2_PLL_REFDIV_SHIFT_MMP3_B0		9
-#define USB2_PLL_VDD18_SHIFT_MMP3_B0		14
-#define USB2_PLL_FBDIV_MASK_MMP3_B0		0x01FF
-#define USB2_PLL_REFDIV_MASK_MMP3_B0		0x3E00
-
-#define USB2_PLL_CAL12_SHIFT_MMP3		0
-#define USB2_PLL_CALI12_MASK_MMP3		(0x3 << 0)
-
-#define USB2_PLL_VCOCAL_START_SHIFT_MMP3	2
-
-#define USB2_PLL_KVCO_SHIFT_MMP3		4
-#define USB2_PLL_KVCO_MASK_MMP3			(0x7<<4)
-
-#define USB2_PLL_ICP_SHIFT_MMP3			8
-#define USB2_PLL_ICP_MASK_MMP3			(0x7<<8)
-
-#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3		12
-
-#define USB2_PLL_PU_PLL_SHIFT_MMP3		13
-#define USB2_PLL_PU_PLL_MASK			(0x1 << 13)
-
-#define USB2_PLL_READY_MASK_MMP3		(0x1 << 15)
-
-/* USB2_TX_REG0 */
-#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3		8
-#define USB2_TX_IMPCAL_VTH_MASK_MMP3		(0x7 << 8)
-
-#define USB2_TX_RCAL_START_SHIFT_MMP3		13
-
-/* USB2_TX_REG1 */
-#define USB2_TX_CK60_PHSEL_SHIFT_MMP3		0
-#define USB2_TX_CK60_PHSEL_MASK_MMP3		(0xf << 0)
-
-#define USB2_TX_AMP_SHIFT_MMP3			4
-#define USB2_TX_AMP_MASK_MMP3			(0x7 << 4)
-
-#define USB2_TX_VDD12_SHIFT_MMP3		8
-#define USB2_TX_VDD12_MASK_MMP3			(0x3 << 8)
-
-/* USB2_TX_REG2 */
-#define USB2_TX_DRV_SLEWRATE_SHIFT		10
-
-/* USB2_RX_REG0 */
-#define USB2_RX_SQ_THRESH_SHIFT_MMP3		4
-#define USB2_RX_SQ_THRESH_MASK_MMP3		(0xf << 4)
-
-#define USB2_RX_SQ_LENGTH_SHIFT_MMP3		10
-#define USB2_RX_SQ_LENGTH_MASK_MMP3		(0x3 << 10)
-
-/* USB2_ANA_REG1*/
-#define USB2_ANA_PU_ANA_SHIFT_MMP3		14
-
-/* USB2_OTG_REG0 */
-#define USB2_OTG_PU_OTG_SHIFT_MMP3		3
-
 /* fsic registers */
 #define FSIC_MISC			0x4
 #define FSIC_INT			0x28
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 15/16] phy: phy-mmp3-usb: add a new driver
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (13 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 14/16] ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-10-10  8:58   ` Kishon Vijay Abraham I
  2019-08-30 22:07 ` [PATCH v3 16/16] ARM: dts: mmp3: Add MMP3 SoC dts file Lubomir Rintel
  2019-09-05 10:24 ` [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Arnd Bergmann
  16 siblings, 1 reply; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

This is the USB2 PHY as found on the Marvell MMP3 SoC. Based on Marvell GPL
release.

While at that, also add a MAINTAINERS entry including the other MMP PHY
driver.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 MAINTAINERS                        |   7 +
 drivers/phy/marvell/Kconfig        |  11 ++
 drivers/phy/marvell/Makefile       |   1 +
 drivers/phy/marvell/phy-mmp3-usb.c | 291 +++++++++++++++++++++++++++++
 4 files changed, 310 insertions(+)
 create mode 100644 drivers/phy/marvell/phy-mmp3-usb.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 176ef19f0b9db..449349f8f20bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10799,6 +10799,13 @@ F:	arch/arm/boot/dts/mmp*
 F:	arch/arm/mach-mmp/
 F:	linux/soc/mmp/
 
+MMP USB PHY DRIVERS
+R:	Lubomir Rintel <lkundrak@v3.sk>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	drivers/phy/marvell/phy-mmp3-usb.c
+F:	drivers/phy/marvell/phy-pxa-usb.c
+
 MMU GATHER AND TLB INVALIDATION
 M:	Will Deacon <will@kernel.org>
 M:	"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
index 0e1642419c0bf..d33ef35b3e51b 100644
--- a/drivers/phy/marvell/Kconfig
+++ b/drivers/phy/marvell/Kconfig
@@ -102,3 +102,14 @@ config PHY_PXA_USB
 	  The PHY driver will be used by Marvell udc/ehci/otg driver.
 
 	  To compile this driver as a module, choose M here.
+
+config PHY_MMP3_USB
+	tristate "Marvell MMP3 USB PHY Driver"
+	depends on MACH_MMP3_DT || COMPILE_TEST
+	select GENERIC_PHY
+	help
+	  Enable this to support Marvell MMP3 USB PHY driver for Marvell
+	  SoC. This driver will do the PHY initialization and shutdown.
+	  The PHY driver will be used by Marvell udc/ehci/otg driver.
+
+	  To compile this driver as a module, choose M here.
diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile
index 434eb9ca6cc3f..5a106b1549f41 100644
--- a/drivers/phy/marvell/Makefile
+++ b/drivers/phy/marvell/Makefile
@@ -2,6 +2,7 @@
 obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)	+= phy-armada375-usb2.o
 obj-$(CONFIG_PHY_BERLIN_SATA)		+= phy-berlin-sata.o
 obj-$(CONFIG_PHY_BERLIN_USB)		+= phy-berlin-usb.o
+obj-$(CONFIG_PHY_MMP3_USB)		+= phy-mmp3-usb.o
 obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY)	+= phy-mvebu-a3700-comphy.o
 obj-$(CONFIG_PHY_MVEBU_A3700_UTMI)	+= phy-mvebu-a3700-utmi.o
 obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY)	+= phy-armada38x-comphy.o
diff --git a/drivers/phy/marvell/phy-mmp3-usb.c b/drivers/phy/marvell/phy-mmp3-usb.c
new file mode 100644
index 0000000000000..499869595a582
--- /dev/null
+++ b/drivers/phy/marvell/phy-mmp3-usb.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+ * Copyright (C) 2018,2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mmp/cputype.h>
+
+#define USB2_PLL_REG0		0x4
+#define USB2_PLL_REG1		0x8
+#define USB2_TX_REG0		0x10
+#define USB2_TX_REG1		0x14
+#define USB2_TX_REG2		0x18
+#define USB2_RX_REG0		0x20
+#define USB2_RX_REG1		0x24
+#define USB2_RX_REG2		0x28
+#define USB2_ANA_REG0		0x30
+#define USB2_ANA_REG1		0x34
+#define USB2_ANA_REG2		0x38
+#define USB2_DIG_REG0		0x3C
+#define USB2_DIG_REG1		0x40
+#define USB2_DIG_REG2		0x44
+#define USB2_DIG_REG3		0x48
+#define USB2_TEST_REG0		0x4C
+#define USB2_TEST_REG1		0x50
+#define USB2_TEST_REG2		0x54
+#define USB2_CHARGER_REG0	0x58
+#define USB2_OTG_REG0		0x5C
+#define USB2_PHY_MON0		0x60
+#define USB2_RESETVE_REG0	0x64
+#define USB2_ICID_REG0		0x78
+#define USB2_ICID_REG1		0x7C
+
+/* USB2_PLL_REG0 */
+
+/* This is for Ax stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3		0
+#define USB2_PLL_FBDIV_MASK_MMP3		(0xFF << 0)
+
+#define USB2_PLL_REFDIV_SHIFT_MMP3		8
+#define USB2_PLL_REFDIV_MASK_MMP3		(0xF << 8)
+
+#define USB2_PLL_VDD12_SHIFT_MMP3		12
+#define USB2_PLL_VDD18_SHIFT_MMP3		14
+
+/* This is for B0 stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3_B0		0
+#define USB2_PLL_REFDIV_SHIFT_MMP3_B0		9
+#define USB2_PLL_VDD18_SHIFT_MMP3_B0		14
+#define USB2_PLL_FBDIV_MASK_MMP3_B0		0x01FF
+#define USB2_PLL_REFDIV_MASK_MMP3_B0		0x3E00
+
+#define USB2_PLL_CAL12_SHIFT_MMP3		0
+#define USB2_PLL_CALI12_MASK_MMP3		(0x3 << 0)
+
+#define USB2_PLL_VCOCAL_START_SHIFT_MMP3	2
+
+#define USB2_PLL_KVCO_SHIFT_MMP3		4
+#define USB2_PLL_KVCO_MASK_MMP3			(0x7<<4)
+
+#define USB2_PLL_ICP_SHIFT_MMP3			8
+#define USB2_PLL_ICP_MASK_MMP3			(0x7<<8)
+
+#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3		12
+
+#define USB2_PLL_PU_PLL_SHIFT_MMP3		13
+#define USB2_PLL_PU_PLL_MASK			(0x1 << 13)
+
+#define USB2_PLL_READY_MASK_MMP3		(0x1 << 15)
+
+/* USB2_TX_REG0 */
+#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3		8
+#define USB2_TX_IMPCAL_VTH_MASK_MMP3		(0x7 << 8)
+
+#define USB2_TX_RCAL_START_SHIFT_MMP3		13
+
+/* USB2_TX_REG1 */
+#define USB2_TX_CK60_PHSEL_SHIFT_MMP3		0
+#define USB2_TX_CK60_PHSEL_MASK_MMP3		(0xf << 0)
+
+#define USB2_TX_AMP_SHIFT_MMP3			4
+#define USB2_TX_AMP_MASK_MMP3			(0x7 << 4)
+
+#define USB2_TX_VDD12_SHIFT_MMP3		8
+#define USB2_TX_VDD12_MASK_MMP3			(0x3 << 8)
+
+/* USB2_TX_REG2 */
+#define USB2_TX_DRV_SLEWRATE_SHIFT		10
+
+/* USB2_RX_REG0 */
+#define USB2_RX_SQ_THRESH_SHIFT_MMP3		4
+#define USB2_RX_SQ_THRESH_MASK_MMP3		(0xf << 4)
+
+#define USB2_RX_SQ_LENGTH_SHIFT_MMP3		10
+#define USB2_RX_SQ_LENGTH_MASK_MMP3		(0x3 << 10)
+
+/* USB2_ANA_REG1*/
+#define USB2_ANA_PU_ANA_SHIFT_MMP3		14
+
+/* USB2_OTG_REG0 */
+#define USB2_OTG_PU_OTG_SHIFT_MMP3		3
+
+struct mmp3_usb_phy {
+	struct phy *phy;
+	void __iomem *base;
+};
+
+static unsigned int u2o_get(void __iomem *base, unsigned int offset)
+{
+	return readl_relaxed(base + offset);
+}
+
+static void u2o_set(void __iomem *base, unsigned int offset,
+		unsigned int value)
+{
+	u32 reg;
+
+	reg = readl_relaxed(base + offset);
+	reg |= value;
+	writel_relaxed(reg, base + offset);
+	readl_relaxed(base + offset);
+}
+
+static void u2o_clear(void __iomem *base, unsigned int offset,
+		unsigned int value)
+{
+	u32 reg;
+
+	reg = readl_relaxed(base + offset);
+	reg &= ~value;
+	writel_relaxed(reg, base + offset);
+	readl_relaxed(base + offset);
+}
+
+static int mmp3_usb_phy_init(struct phy *phy)
+{
+	struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
+	void __iomem *base = mmp3_usb_phy->base;
+
+	if (cpu_is_mmp3_a0()) {
+		u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3
+			| USB2_PLL_REFDIV_MASK_MMP3));
+		u2o_set(base, USB2_PLL_REG0,
+			0xd << USB2_PLL_REFDIV_SHIFT_MMP3
+			| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3);
+	} else if (cpu_is_mmp3_b0()) {
+		u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0
+			| USB2_PLL_FBDIV_MASK_MMP3_B0);
+		u2o_set(base, USB2_PLL_REG0,
+			0xd << USB2_PLL_REFDIV_SHIFT_MMP3_B0
+			| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3_B0);
+	} else {
+		dev_err(&phy->dev, "unsupported silicon revision\n");
+		return -ENODEV;
+	}
+
+	u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK
+		| USB2_PLL_ICP_MASK_MMP3
+		| USB2_PLL_KVCO_MASK_MMP3
+		| USB2_PLL_CALI12_MASK_MMP3);
+	u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3
+		| 1 << USB2_PLL_LOCK_BYPASS_SHIFT_MMP3
+		| 3 << USB2_PLL_ICP_SHIFT_MMP3
+		| 3 << USB2_PLL_KVCO_SHIFT_MMP3
+		| 3 << USB2_PLL_CAL12_SHIFT_MMP3);
+
+	u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3);
+	u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3);
+
+	u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3
+		| USB2_TX_AMP_MASK_MMP3
+		| USB2_TX_CK60_PHSEL_MASK_MMP3);
+	u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3
+		| 4 << USB2_TX_AMP_SHIFT_MMP3
+		| 4 << USB2_TX_CK60_PHSEL_SHIFT_MMP3);
+
+	u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT);
+	u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT);
+
+	u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3);
+	u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3);
+
+	u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3);
+
+	u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3);
+
+	return 0;
+}
+
+static int mmp3_usb_phy_calibrate(struct phy *phy)
+{
+	struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
+	void __iomem *base = mmp3_usb_phy->base;
+	int loops;
+
+	/*
+	 * PLL VCO and TX Impedance Calibration Timing:
+	 *
+	 *                _____________________________________
+	 * PU  __________|
+	 *                        _____________________________
+	 * VCOCAL START _________|
+	 *                                 ___
+	 * REG_RCAL_START ________________|   |________|_______
+	 *               | 200us | 400us  | 40| 400us  | USB PHY READY
+	 */
+
+	udelay(200);
+	u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3);
+	udelay(400);
+	u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
+	udelay(40);
+	u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
+	udelay(400);
+
+	loops = 0;
+	while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) {
+		mdelay(1);
+		loops++;
+		if (loops > 100) {
+			dev_err(&phy->dev, "PLL_READY not set after 100mS.\n");
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static const struct phy_ops mmp3_usb_phy_ops = {
+	.init		= mmp3_usb_phy_init,
+	.calibrate	= mmp3_usb_phy_calibrate,
+	.owner		= THIS_MODULE,
+};
+
+static const struct of_device_id mmp3_usb_phy_of_match[] = {
+	{ .compatible = "marvell,mmp3-usb-phy", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mmp3_usb_phy_of_match);
+
+static int mmp3_usb_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *resource;
+	struct mmp3_usb_phy *mmp3_usb_phy;
+	struct phy_provider *provider;
+
+	mmp3_usb_phy = devm_kzalloc(dev, sizeof(*mmp3_usb_phy), GFP_KERNEL);
+	if (!mmp3_usb_phy)
+		return -ENOMEM;
+
+	resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mmp3_usb_phy->base = devm_ioremap_resource(dev, resource);
+	if (IS_ERR(mmp3_usb_phy->base)) {
+		dev_err(dev, "failed to remap PHY regs\n");
+		return PTR_ERR(mmp3_usb_phy->base);
+	}
+
+	mmp3_usb_phy->phy = devm_phy_create(dev, NULL, &mmp3_usb_phy_ops);
+	if (IS_ERR(mmp3_usb_phy->phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(mmp3_usb_phy->phy);
+	}
+
+	phy_set_drvdata(mmp3_usb_phy->phy, mmp3_usb_phy);
+	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(provider)) {
+		dev_err(dev, "failed to register PHY provider\n");
+		return PTR_ERR(provider);
+	}
+
+	return 0;
+}
+
+static struct platform_driver mmp3_usb_phy_driver = {
+	.probe		= mmp3_usb_phy_probe,
+	.driver		= {
+		.name	= "mmp3-usb-phy",
+		.of_match_table = mmp3_usb_phy_of_match,
+	},
+};
+module_platform_driver(mmp3_usb_phy_driver);
+
+MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
+MODULE_DESCRIPTION("Marvell MMP3 USB PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v3 16/16] ARM: dts: mmp3: Add MMP3 SoC dts file
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (14 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 15/16] phy: phy-mmp3-usb: add a new driver Lubomir Rintel
@ 2019-08-30 22:07 ` Lubomir Rintel
  2019-09-05 10:17   ` Arnd Bergmann
  2019-09-05 10:24 ` [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Arnd Bergmann
  16 siblings, 1 reply; 24+ messages in thread
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
  To: To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	Stephen Boyd, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, Lubomir Rintel

Describes most of the hardware found on Marvell MMP3, aka PXA2128, aka
Armada 620. Missing bits are the LCD controller, HSIC controllers,
Audio and GPU. Will be completed once bindings and drivers settle.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 arch/arm/boot/dts/mmp3.dtsi | 534 ++++++++++++++++++++++++++++++++++++
 1 file changed, 534 insertions(+)
 create mode 100644 arch/arm/boot/dts/mmp3.dtsi

diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi
new file mode 100644
index 0000000000000..5a6275257ebdd
--- /dev/null
+++ b/arch/arm/boot/dts/mmp3.dtsi
@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ *  Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+#include <dt-bindings/clock/marvell,mmp2.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "marvell,mmp3-smp";
+
+		cpu@0 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <1>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		axi@d4200000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			interrupt-controller@d4282000 {
+				compatible = "marvell,mmp3-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xd4282000 0x1000>,
+				      <0xd4284000 0x100>;
+				mrvl,intc-nr-irqs = <64>;
+			};
+
+			pmic_mux: interrupt-controller@d4282150 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x150 0x4>, <0x168 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <4>;
+			};
+
+			rtc_mux: interrupt-controller@d4282154 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x154 0x4>, <0x16c 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			hsi3_mux: interrupt-controller@d42821bc {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x1bc 0x4>, <0x1a4 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <3>;
+			};
+
+			gpu_mux: interrupt-controller@d42821c0 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x1c0 0x4>, <0x1a8 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <3>;
+			};
+
+			twsi_mux: interrupt-controller@d4282158 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x158 0x4>, <0x170 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <5>;
+			};
+
+			hsi2_mux: interrupt-controller@d42821c4 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x1c4 0x4>, <0x1ac 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			dxo_mux: interrupt-controller@d42821c8 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x1c8 0x4>, <0x1b0 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			misc1_mux: interrupt-controller@d428215c {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x15c 0x4>, <0x174 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <31>;
+			};
+
+			ci_mux: interrupt-controller@d42821cc {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x1cc 0x4>, <0x1b4 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			ssp_mux: interrupt-controller@d4282160 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x160 0x4>, <0x178 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			hsi1_mux: interrupt-controller@d4282184 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x184 0x4>, <0x17c 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <4>;
+			};
+
+			misc2_mux: interrupt-controller@d4282188 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x188 0x4>, <0x180 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <20>;
+			};
+
+			hsi0_mux: interrupt-controller@d42821d0 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x1d0 0x4>, <0x1b8 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <5>;
+			};
+
+			usb_otg_phy0: usb-otg-phy@d4207000 {
+				compatible = "marvell,mmp3-usb-phy";
+				reg = <0xd4207000 0x40>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
+			usb_otg0: usb-otg@d4208000 {
+				compatible = "marvell,pxau2o-ehci";
+				reg = <0xd4208000 0x200>;
+				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_USB>;
+				clock-names = "USBCLK";
+				phys = <&usb_otg_phy0>;
+				phy-names = "usb";
+				status = "disabled";
+			};
+
+			mmc1: mmc@d4280000 {
+				compatible = "mrvl,pxav3-mmc";
+				reg = <0xd4280000 0x120>;
+				clocks = <&soc_clocks MMP2_CLK_SDH0>;
+				clock-names = "io";
+				interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			mmc2: mmc@d4280800 {
+				compatible = "mrvl,pxav3-mmc";
+				reg = <0xd4280800 0x120>;
+				clocks = <&soc_clocks MMP2_CLK_SDH1>;
+				clock-names = "io";
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			mmc3: mmc@d4281000 {
+				compatible = "mrvl,pxav3-mmc";
+				reg = <0xd4281000 0x120>;
+				clocks = <&soc_clocks MMP2_CLK_SDH2>;
+				clock-names = "io";
+				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			mmc4: mmc@d4281800 {
+				compatible = "mrvl,pxav3-mmc";
+				reg = <0xd4281800 0x120>;
+				clocks = <&soc_clocks MMP2_CLK_SDH3>;
+				clock-names = "io";
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			camera0: camera@d420a000 {
+				compatible = "marvell,mmp2-ccic";
+				reg = <0xd420a000 0x800>;
+				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_CCIC0>;
+				clock-names = "axi";
+				#clock-cells = <0>;
+				clock-output-names = "mclk";
+				status = "disabled";
+			};
+
+			camera1: camera@d420a800 {
+				compatible = "marvell,mmp2-ccic";
+				reg = <0xd420a800 0x800>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_CCIC1>;
+				clock-names = "axi";
+				#clock-cells = <0>;
+				clock-output-names = "mclk";
+				status = "disabled";
+			};
+		};
+
+		apb@d4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			timer: timer@d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_TIMER>;
+			};
+
+			uart1: uart@d4030000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4030000 0x1000>;
+				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_UART0>;
+				resets = <&soc_clocks MMP2_CLK_UART0>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			uart2: uart@d4017000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_UART1>;
+				resets = <&soc_clocks MMP2_CLK_UART1>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			uart3: uart@d4018000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_UART2>;
+				resets = <&soc_clocks MMP2_CLK_UART2>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			uart4: uart@d4016000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4016000 0x1000>;
+				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_UART3>;
+				resets = <&soc_clocks MMP2_CLK_UART3>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			gpio: gpio@d4019000 {
+				compatible = "marvell,mmp2-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "gpio_mux";
+				clocks = <&soc_clocks MMP2_CLK_GPIO>;
+				resets = <&soc_clocks MMP2_CLK_GPIO>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ranges;
+
+				gcb0: gpio@d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio@d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio@d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio@d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
+
+				gcb4: gpio@d4019104 {
+					reg = <0xd4019104 0x4>;
+				};
+
+				gcb5: gpio@d4019108 {
+					reg = <0xd4019108 0x4>;
+				};
+			};
+
+			twsi1: i2c@d4011000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4011000 0x1000>;
+				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&soc_clocks MMP2_CLK_TWSI0>;
+				resets = <&soc_clocks MMP2_CLK_TWSI0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c@d4031000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4031000 0x1000>;
+				interrupt-parent = <&twsi_mux>;
+				interrupts = <0>;
+				clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+				resets = <&soc_clocks MMP2_CLK_TWSI1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			twsi3: i2c@d4032000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4032000 0x1000>;
+				interrupt-parent = <&twsi_mux>;
+				interrupts = <1>;
+				clocks = <&soc_clocks MMP2_CLK_TWSI2>;
+				resets = <&soc_clocks MMP2_CLK_TWSI2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			twsi4: i2c@d4033000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4033000 0x1000>;
+				interrupt-parent = <&twsi_mux>;
+				interrupts = <2>;
+				clocks = <&soc_clocks MMP2_CLK_TWSI3>;
+				resets = <&soc_clocks MMP2_CLK_TWSI3>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+
+			twsi5: i2c@d4033800 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4033800 0x1000>;
+				interrupt-parent = <&twsi_mux>;
+				interrupts = <3>;
+				clocks = <&soc_clocks MMP2_CLK_TWSI4>;
+				resets = <&soc_clocks MMP2_CLK_TWSI4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			twsi6: i2c@d4034000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4034000 0x1000>;
+				interrupt-parent = <&twsi_mux>;
+				interrupts = <4>;
+				clocks = <&soc_clocks MMP2_CLK_TWSI5>;
+				resets = <&soc_clocks MMP2_CLK_TWSI5>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			rtc: rtc@d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <1 0>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				interrupt-parent = <&rtc_mux>;
+				clocks = <&soc_clocks MMP2_CLK_RTC>;
+				resets = <&soc_clocks MMP2_CLK_RTC>;
+				status = "disabled";
+			};
+
+			ssp1: spi@d4035000 {
+				compatible = "marvell,mmp2-ssp";
+				reg = <0xd4035000 0x1000>;
+				clocks = <&soc_clocks MMP2_CLK_SSP0>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			ssp2: spi@d4036000 {
+				compatible = "marvell,mmp2-ssp";
+				reg = <0xd4036000 0x1000>;
+				clocks = <&soc_clocks MMP2_CLK_SSP1>;
+				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			ssp3: spi@d4037000 {
+				compatible = "marvell,mmp2-ssp";
+				reg = <0xd4037000 0x1000>;
+				clocks = <&soc_clocks MMP2_CLK_SSP2>;
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			ssp4: spi@d4039000 {
+				compatible = "marvell,mmp2-ssp";
+				reg = <0xd4039000 0x1000>;
+				clocks = <&soc_clocks MMP2_CLK_SSP3>;
+				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
+		l2: l2-cache-controller@d0020000 {
+			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+			reg = <0xd0020000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		soc_clocks: clocks {
+			compatible = "marvell,mmp2-clock";
+			reg = <0xd4050000 0x1000>,
+			      <0xd4282800 0x400>,
+			      <0xd4015000 0x1000>;
+			reg-names = "mpmu", "apmu", "apbc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		snoop-control-unit@e0000000 {
+			compatible = "arm,arm11mp-scu";
+			reg = <0xe0000000 0x100>;
+		};
+
+		gic: interrupt-controller@e0001000 {
+			compatible = "arm,arm11mp-gic";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0xe0001000 0x1000>,
+			      <0xe0000100 0x100>;
+		};
+
+		local-timer@e0000600 {
+			compatible = "arm,arm11mp-twd-timer";
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+						  IRQ_TYPE_EDGE_RISING)>;
+			reg = <0xe0000600 0x20>;
+		};
+
+		watchdog@2c000620 {
+			compatible = "arm,arm11mp-twd-wdt";
+			reg = <0xe0000620 0x20>;
+			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+						  IRQ_TYPE_EDGE_RISING)>;
+		};
+	};
+};
-- 
2.21.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v3 13/16] ARM: mmp: move cputype.h to include/linux/soc/
  2019-08-30 22:07 ` [PATCH v3 13/16] ARM: mmp: move cputype.h to include/linux/soc/ Lubomir Rintel
@ 2019-09-02  8:15   ` kbuild test robot
  2019-09-05 10:20     ` Arnd Bergmann
  0 siblings, 1 reply; 24+ messages in thread
From: kbuild test robot @ 2019-09-02  8:15 UTC (permalink / raw)
  To: Lubomir Rintel
  Cc: kbuild-all, To : Olof Johansson, Cc : Rob Herring, Mark Rutland,
	Thomas Gleixner, Jason Cooper, Kishon Vijay Abraham I,
	Russell King, Michael Turquette, Stephen Boyd, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, Lubomir Rintel

[-- Attachment #1: Type: text/plain, Size: 1705 bytes --]

Hi Lubomir,

I love your patch! Yet something to improve:

[auto build test ERROR on arm/for-next]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Lubomir-Rintel/Initial-support-for-Marvell-MMP3-SoC/20190901-110305
base:   git://git.armlinux.org.uk/~rmk/linux-arm.git for-next
config: x86_64-randconfig-s2-09021304 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   In file included from <command-line>:0:0:
>> include/linux/soc/mmp/cputype.h:5:10: fatal error: asm/cputype.h: No such file or directory
    #include <asm/cputype.h>
             ^~~~~~~~~~~~~~~
   compilation terminated.

vim +5 include/linux/soc/mmp/cputype.h

49cbe78637eb05 arch/arm/mach-mmp/include/mach/cputype.h Eric Miao 2009-01-20  4  
49cbe78637eb05 arch/arm/mach-mmp/include/mach/cputype.h Eric Miao 2009-01-20 @5  #include <asm/cputype.h>
49cbe78637eb05 arch/arm/mach-mmp/include/mach/cputype.h Eric Miao 2009-01-20  6  

:::::: The code at line 5 was first introduced by commit
:::::: 49cbe78637eb0503f45fc9b556ec08918a616534 [ARM] pxa: add base support for Marvell's PXA168 processor line

:::::: TO: Eric Miao <eric.miao@marvell.com>
:::::: CC: Eric Miao <eric.miao@marvell.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 33158 bytes --]

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v3 02/16] dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema
  2019-08-30 22:07 ` [PATCH v3 02/16] dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema Lubomir Rintel
@ 2019-09-02 13:39   ` Rob Herring
  0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2019-09-02 13:39 UTC (permalink / raw)
  To: Lubomir Rintel; +Cc: To : Olof Johansson

On Sat, 31 Aug 2019 00:07:29 +0200, Lubomir Rintel wrote:
> Convert Marvell MMP SoC bindings to DT schema format using json-schema.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> 
> ---
> Changes since v2:
> - Add mrvl,pxa910
> - s/MMP2 Brownstone Board/MMP2 based boards/
> 
> Changes since v1:
> - Added this patch
> 
>  .../devicetree/bindings/arm/mrvl/mrvl.txt     | 14 --------
>  .../devicetree/bindings/arm/mrvl/mrvl.yaml    | 32 +++++++++++++++++++
>  2 files changed, 32 insertions(+), 14 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>


^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v3 16/16] ARM: dts: mmp3: Add MMP3 SoC dts file
  2019-08-30 22:07 ` [PATCH v3 16/16] ARM: dts: mmp3: Add MMP3 SoC dts file Lubomir Rintel
@ 2019-09-05 10:17   ` Arnd Bergmann
  0 siblings, 0 replies; 24+ messages in thread
From: Arnd Bergmann @ 2019-09-05 10:17 UTC (permalink / raw)
  To: Lubomir Rintel
  Cc: To : Olof Johansson, Mark Rutland, DTML, Jason Cooper,
	Stephen Boyd, linux-kernel, Michael Turquette, Russell King,
	Kishon Vijay Abraham I, Cc : Rob Herring, Thomas Gleixner,
	linux-clk, Linux ARM

On Sat, Aug 31, 2019 at 12:12 AM Lubomir Rintel <lkundrak@v3.sk> wrote:

> +/ {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +
> +       aliases {
> +               serial0 = &uart1;
> +               serial1 = &uart2;
> +               serial2 = &uart3;
> +               serial3 = &uart4;
> +       };

Better move the aliases into the per-board file, not every board
would have all four uarts connected, or labeled in that particular
order.

        Arnd

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v3 13/16] ARM: mmp: move cputype.h to include/linux/soc/
  2019-09-02  8:15   ` kbuild test robot
@ 2019-09-05 10:20     ` Arnd Bergmann
  0 siblings, 0 replies; 24+ messages in thread
From: Arnd Bergmann @ 2019-09-05 10:20 UTC (permalink / raw)
  To: kbuild test robot
  Cc: Lubomir Rintel, Mark Rutland, DTML, Jason Cooper, Stephen Boyd,
	linux-kernel, Michael Turquette, Russell King,
	Kishon Vijay Abraham I, Cc : Rob Herring, kbuild-all,
	To : Olof Johansson, Thomas Gleixner, linux-clk, Linux ARM

On Mon, Sep 2, 2019 at 10:16 AM kbuild test robot <lkp@intel.com> wrote:

>
> vim +5 include/linux/soc/mmp/cputype.h
>
> 49cbe78637eb05 arch/arm/mach-mmp/include/mach/cputype.h Eric Miao 2009-01-20  4
> 49cbe78637eb05 arch/arm/mach-mmp/include/mach/cputype.h Eric Miao 2009-01-20 @5  #include <asm/cputype.h>
> 49cbe78637eb05 arch/arm/mach-mmp/include/mach/cputype.h Eric Miao 2009-01-20  6
>

You can probably do something like

#ifdef CONFIG_ARM
#include <asm/cputype.h>
#else
static inline read_cpuid_id(void) { return 0; }
#endif

Then again, ideally drivers don't even have to know about this,
but would distinguish between devices based on the
compatible string for the particular device.

       Arnd

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v3 00/16] Initial support for Marvell MMP3 SoC
  2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
                   ` (15 preceding siblings ...)
  2019-08-30 22:07 ` [PATCH v3 16/16] ARM: dts: mmp3: Add MMP3 SoC dts file Lubomir Rintel
@ 2019-09-05 10:24 ` Arnd Bergmann
  16 siblings, 0 replies; 24+ messages in thread
From: Arnd Bergmann @ 2019-09-05 10:24 UTC (permalink / raw)
  To: Lubomir Rintel
  Cc: To : Olof Johansson, Mark Rutland, DTML, Jason Cooper,
	Stephen Boyd, linux-kernel, Michael Turquette, Russell King,
	Kishon Vijay Abraham I, Cc : Rob Herring, Thomas Gleixner,
	linux-clk, Linux ARM

On Sat, Aug 31, 2019 at 12:08 AM Lubomir Rintel <lkundrak@v3.sk> wrote:
>
> this is the third spin of a patch set that adds support for the Marvell
> MMP3 processor, that I'd eventually love to see land in the Arm SoC
> tree. MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet
> and Dell Wyse 3020/Tx0D thin clients.
>
> Compared to v2, there's a handful of fixes in response to reviews. Four
> irqchip patches have been removed because they've been applied to the
> irqchip-next tree. Details in individual patches.

I just looked at the series, looks great overall, but the timing means
this is going to be 5.5 material by now. Please send a pull request
to soc@kernel.org cc:lakml after -rc1 is out.

I replied with a couple of comments for details I noticed.

       Arnd

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v3 11/16] ARM: mmp: add support for MMP3 SoC
  2019-08-30 22:07 ` [PATCH v3 11/16] ARM: mmp: add support for MMP3 SoC Lubomir Rintel
@ 2019-09-06 23:48   ` Stephen Boyd
  0 siblings, 0 replies; 24+ messages in thread
From: Stephen Boyd @ 2019-09-06 23:48 UTC (permalink / raw)
  To: To : Olof Johansson, Lubomir Rintel
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Kishon Vijay Abraham I, Russell King, Michael Turquette,
	devicetree, linux-kernel, linux-arm-kernel, linux-clk,
	Lubomir Rintel

Quoting Lubomir Rintel (2019-08-30 15:07:38)
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 801fa1cd03217..8bb2ac83a1fcc 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -301,6 +301,11 @@ config COMMON_CLK_STM32H7
>         ---help---
>           Support for stm32h7 SoC family clocks
>  
> +config COMMON_CLK_MMP2
> +       def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)

Does it need to depend on COMMON_CLK? I thought that by being part of
the menuconfig (even if it's a hidden symbol) mean that it wouldn't be
evaulated unless the COMMON_CLK define is =Y.

> +       help
> +         Support for Marvell MMP2 and MMP3 SoC clocks
> +
>  config COMMON_CLK_BD718XX
>         tristate "Clock driver for ROHM BD718x7 PMIC"
>         depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v3 15/16] phy: phy-mmp3-usb: add a new driver
  2019-08-30 22:07 ` [PATCH v3 15/16] phy: phy-mmp3-usb: add a new driver Lubomir Rintel
@ 2019-10-10  8:58   ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2019-10-10  8:58 UTC (permalink / raw)
  To: Lubomir Rintel, To : Olof Johansson
  Cc: Cc : Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Russell King, Michael Turquette, Stephen Boyd, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk

Hi,

On 31/08/19 3:37 AM, Lubomir Rintel wrote:

Change the $subject to "phy: Add USB2 PHY driver for Marvell MMP3 SoC"
> This is the USB2 PHY as found on the Marvell MMP3 SoC. Based on Marvell GPL
> release.

Just have "Add PHY driver for the USB2 PHY found on Marvell MMP3 SoC." here.
> 
> While at that, also add a MAINTAINERS entry including the other MMP PHY
> driver.

Adding MAINTAINERS could be a different patch.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

Once the commit log is fixed:
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Thanks
Kishon
> ---
>  MAINTAINERS                        |   7 +
>  drivers/phy/marvell/Kconfig        |  11 ++
>  drivers/phy/marvell/Makefile       |   1 +
>  drivers/phy/marvell/phy-mmp3-usb.c | 291 +++++++++++++++++++++++++++++
>  4 files changed, 310 insertions(+)
>  create mode 100644 drivers/phy/marvell/phy-mmp3-usb.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 176ef19f0b9db..449349f8f20bf 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -10799,6 +10799,13 @@ F:	arch/arm/boot/dts/mmp*
>  F:	arch/arm/mach-mmp/
>  F:	linux/soc/mmp/
>  
> +MMP USB PHY DRIVERS
> +R:	Lubomir Rintel <lkundrak@v3.sk>
> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S:	Maintained
> +F:	drivers/phy/marvell/phy-mmp3-usb.c
> +F:	drivers/phy/marvell/phy-pxa-usb.c
> +
>  MMU GATHER AND TLB INVALIDATION
>  M:	Will Deacon <will@kernel.org>
>  M:	"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
> diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
> index 0e1642419c0bf..d33ef35b3e51b 100644
> --- a/drivers/phy/marvell/Kconfig
> +++ b/drivers/phy/marvell/Kconfig
> @@ -102,3 +102,14 @@ config PHY_PXA_USB
>  	  The PHY driver will be used by Marvell udc/ehci/otg driver.
>  
>  	  To compile this driver as a module, choose M here.
> +
> +config PHY_MMP3_USB
> +	tristate "Marvell MMP3 USB PHY Driver"
> +	depends on MACH_MMP3_DT || COMPILE_TEST
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support Marvell MMP3 USB PHY driver for Marvell
> +	  SoC. This driver will do the PHY initialization and shutdown.
> +	  The PHY driver will be used by Marvell udc/ehci/otg driver.
> +
> +	  To compile this driver as a module, choose M here.
> diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile
> index 434eb9ca6cc3f..5a106b1549f41 100644
> --- a/drivers/phy/marvell/Makefile
> +++ b/drivers/phy/marvell/Makefile
> @@ -2,6 +2,7 @@
>  obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)	+= phy-armada375-usb2.o
>  obj-$(CONFIG_PHY_BERLIN_SATA)		+= phy-berlin-sata.o
>  obj-$(CONFIG_PHY_BERLIN_USB)		+= phy-berlin-usb.o
> +obj-$(CONFIG_PHY_MMP3_USB)		+= phy-mmp3-usb.o
>  obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY)	+= phy-mvebu-a3700-comphy.o
>  obj-$(CONFIG_PHY_MVEBU_A3700_UTMI)	+= phy-mvebu-a3700-utmi.o
>  obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY)	+= phy-armada38x-comphy.o
> diff --git a/drivers/phy/marvell/phy-mmp3-usb.c b/drivers/phy/marvell/phy-mmp3-usb.c
> new file mode 100644
> index 0000000000000..499869595a582
> --- /dev/null
> +++ b/drivers/phy/marvell/phy-mmp3-usb.c
> @@ -0,0 +1,291 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
> + * Copyright (C) 2018,2019 Lubomir Rintel <lkundrak@v3.sk>
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mmp/cputype.h>
> +
> +#define USB2_PLL_REG0		0x4
> +#define USB2_PLL_REG1		0x8
> +#define USB2_TX_REG0		0x10
> +#define USB2_TX_REG1		0x14
> +#define USB2_TX_REG2		0x18
> +#define USB2_RX_REG0		0x20
> +#define USB2_RX_REG1		0x24
> +#define USB2_RX_REG2		0x28
> +#define USB2_ANA_REG0		0x30
> +#define USB2_ANA_REG1		0x34
> +#define USB2_ANA_REG2		0x38
> +#define USB2_DIG_REG0		0x3C
> +#define USB2_DIG_REG1		0x40
> +#define USB2_DIG_REG2		0x44
> +#define USB2_DIG_REG3		0x48
> +#define USB2_TEST_REG0		0x4C
> +#define USB2_TEST_REG1		0x50
> +#define USB2_TEST_REG2		0x54
> +#define USB2_CHARGER_REG0	0x58
> +#define USB2_OTG_REG0		0x5C
> +#define USB2_PHY_MON0		0x60
> +#define USB2_RESETVE_REG0	0x64
> +#define USB2_ICID_REG0		0x78
> +#define USB2_ICID_REG1		0x7C
> +
> +/* USB2_PLL_REG0 */
> +
> +/* This is for Ax stepping */
> +#define USB2_PLL_FBDIV_SHIFT_MMP3		0
> +#define USB2_PLL_FBDIV_MASK_MMP3		(0xFF << 0)
> +
> +#define USB2_PLL_REFDIV_SHIFT_MMP3		8
> +#define USB2_PLL_REFDIV_MASK_MMP3		(0xF << 8)
> +
> +#define USB2_PLL_VDD12_SHIFT_MMP3		12
> +#define USB2_PLL_VDD18_SHIFT_MMP3		14
> +
> +/* This is for B0 stepping */
> +#define USB2_PLL_FBDIV_SHIFT_MMP3_B0		0
> +#define USB2_PLL_REFDIV_SHIFT_MMP3_B0		9
> +#define USB2_PLL_VDD18_SHIFT_MMP3_B0		14
> +#define USB2_PLL_FBDIV_MASK_MMP3_B0		0x01FF
> +#define USB2_PLL_REFDIV_MASK_MMP3_B0		0x3E00
> +
> +#define USB2_PLL_CAL12_SHIFT_MMP3		0
> +#define USB2_PLL_CALI12_MASK_MMP3		(0x3 << 0)
> +
> +#define USB2_PLL_VCOCAL_START_SHIFT_MMP3	2
> +
> +#define USB2_PLL_KVCO_SHIFT_MMP3		4
> +#define USB2_PLL_KVCO_MASK_MMP3			(0x7<<4)
> +
> +#define USB2_PLL_ICP_SHIFT_MMP3			8
> +#define USB2_PLL_ICP_MASK_MMP3			(0x7<<8)
> +
> +#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3		12
> +
> +#define USB2_PLL_PU_PLL_SHIFT_MMP3		13
> +#define USB2_PLL_PU_PLL_MASK			(0x1 << 13)
> +
> +#define USB2_PLL_READY_MASK_MMP3		(0x1 << 15)
> +
> +/* USB2_TX_REG0 */
> +#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3		8
> +#define USB2_TX_IMPCAL_VTH_MASK_MMP3		(0x7 << 8)
> +
> +#define USB2_TX_RCAL_START_SHIFT_MMP3		13
> +
> +/* USB2_TX_REG1 */
> +#define USB2_TX_CK60_PHSEL_SHIFT_MMP3		0
> +#define USB2_TX_CK60_PHSEL_MASK_MMP3		(0xf << 0)
> +
> +#define USB2_TX_AMP_SHIFT_MMP3			4
> +#define USB2_TX_AMP_MASK_MMP3			(0x7 << 4)
> +
> +#define USB2_TX_VDD12_SHIFT_MMP3		8
> +#define USB2_TX_VDD12_MASK_MMP3			(0x3 << 8)
> +
> +/* USB2_TX_REG2 */
> +#define USB2_TX_DRV_SLEWRATE_SHIFT		10
> +
> +/* USB2_RX_REG0 */
> +#define USB2_RX_SQ_THRESH_SHIFT_MMP3		4
> +#define USB2_RX_SQ_THRESH_MASK_MMP3		(0xf << 4)
> +
> +#define USB2_RX_SQ_LENGTH_SHIFT_MMP3		10
> +#define USB2_RX_SQ_LENGTH_MASK_MMP3		(0x3 << 10)
> +
> +/* USB2_ANA_REG1*/
> +#define USB2_ANA_PU_ANA_SHIFT_MMP3		14
> +
> +/* USB2_OTG_REG0 */
> +#define USB2_OTG_PU_OTG_SHIFT_MMP3		3
> +
> +struct mmp3_usb_phy {
> +	struct phy *phy;
> +	void __iomem *base;
> +};
> +
> +static unsigned int u2o_get(void __iomem *base, unsigned int offset)
> +{
> +	return readl_relaxed(base + offset);
> +}
> +
> +static void u2o_set(void __iomem *base, unsigned int offset,
> +		unsigned int value)
> +{
> +	u32 reg;
> +
> +	reg = readl_relaxed(base + offset);
> +	reg |= value;
> +	writel_relaxed(reg, base + offset);
> +	readl_relaxed(base + offset);
> +}
> +
> +static void u2o_clear(void __iomem *base, unsigned int offset,
> +		unsigned int value)
> +{
> +	u32 reg;
> +
> +	reg = readl_relaxed(base + offset);
> +	reg &= ~value;
> +	writel_relaxed(reg, base + offset);
> +	readl_relaxed(base + offset);
> +}
> +
> +static int mmp3_usb_phy_init(struct phy *phy)
> +{
> +	struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
> +	void __iomem *base = mmp3_usb_phy->base;
> +
> +	if (cpu_is_mmp3_a0()) {
> +		u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3
> +			| USB2_PLL_REFDIV_MASK_MMP3));
> +		u2o_set(base, USB2_PLL_REG0,
> +			0xd << USB2_PLL_REFDIV_SHIFT_MMP3
> +			| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3);
> +	} else if (cpu_is_mmp3_b0()) {
> +		u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0
> +			| USB2_PLL_FBDIV_MASK_MMP3_B0);
> +		u2o_set(base, USB2_PLL_REG0,
> +			0xd << USB2_PLL_REFDIV_SHIFT_MMP3_B0
> +			| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3_B0);
> +	} else {
> +		dev_err(&phy->dev, "unsupported silicon revision\n");
> +		return -ENODEV;
> +	}
> +
> +	u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK
> +		| USB2_PLL_ICP_MASK_MMP3
> +		| USB2_PLL_KVCO_MASK_MMP3
> +		| USB2_PLL_CALI12_MASK_MMP3);
> +	u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3
> +		| 1 << USB2_PLL_LOCK_BYPASS_SHIFT_MMP3
> +		| 3 << USB2_PLL_ICP_SHIFT_MMP3
> +		| 3 << USB2_PLL_KVCO_SHIFT_MMP3
> +		| 3 << USB2_PLL_CAL12_SHIFT_MMP3);
> +
> +	u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3);
> +	u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3);
> +
> +	u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3
> +		| USB2_TX_AMP_MASK_MMP3
> +		| USB2_TX_CK60_PHSEL_MASK_MMP3);
> +	u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3
> +		| 4 << USB2_TX_AMP_SHIFT_MMP3
> +		| 4 << USB2_TX_CK60_PHSEL_SHIFT_MMP3);
> +
> +	u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT);
> +	u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT);
> +
> +	u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3);
> +	u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3);
> +
> +	u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3);
> +
> +	u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3);
> +
> +	return 0;
> +}
> +
> +static int mmp3_usb_phy_calibrate(struct phy *phy)
> +{
> +	struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
> +	void __iomem *base = mmp3_usb_phy->base;
> +	int loops;
> +
> +	/*
> +	 * PLL VCO and TX Impedance Calibration Timing:
> +	 *
> +	 *                _____________________________________
> +	 * PU  __________|
> +	 *                        _____________________________
> +	 * VCOCAL START _________|
> +	 *                                 ___
> +	 * REG_RCAL_START ________________|   |________|_______
> +	 *               | 200us | 400us  | 40| 400us  | USB PHY READY
> +	 */
> +
> +	udelay(200);
> +	u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3);
> +	udelay(400);
> +	u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
> +	udelay(40);
> +	u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
> +	udelay(400);
> +
> +	loops = 0;
> +	while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) {
> +		mdelay(1);
> +		loops++;
> +		if (loops > 100) {
> +			dev_err(&phy->dev, "PLL_READY not set after 100mS.\n");
> +			return -ETIMEDOUT;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops mmp3_usb_phy_ops = {
> +	.init		= mmp3_usb_phy_init,
> +	.calibrate	= mmp3_usb_phy_calibrate,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static const struct of_device_id mmp3_usb_phy_of_match[] = {
> +	{ .compatible = "marvell,mmp3-usb-phy", },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, mmp3_usb_phy_of_match);
> +
> +static int mmp3_usb_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct resource *resource;
> +	struct mmp3_usb_phy *mmp3_usb_phy;
> +	struct phy_provider *provider;
> +
> +	mmp3_usb_phy = devm_kzalloc(dev, sizeof(*mmp3_usb_phy), GFP_KERNEL);
> +	if (!mmp3_usb_phy)
> +		return -ENOMEM;
> +
> +	resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	mmp3_usb_phy->base = devm_ioremap_resource(dev, resource);
> +	if (IS_ERR(mmp3_usb_phy->base)) {
> +		dev_err(dev, "failed to remap PHY regs\n");
> +		return PTR_ERR(mmp3_usb_phy->base);
> +	}
> +
> +	mmp3_usb_phy->phy = devm_phy_create(dev, NULL, &mmp3_usb_phy_ops);
> +	if (IS_ERR(mmp3_usb_phy->phy)) {
> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(mmp3_usb_phy->phy);
> +	}
> +
> +	phy_set_drvdata(mmp3_usb_phy->phy, mmp3_usb_phy);
> +	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(provider)) {
> +		dev_err(dev, "failed to register PHY provider\n");
> +		return PTR_ERR(provider);
> +	}
> +
> +	return 0;
> +}
> +
> +static struct platform_driver mmp3_usb_phy_driver = {
> +	.probe		= mmp3_usb_phy_probe,
> +	.driver		= {
> +		.name	= "mmp3-usb-phy",
> +		.of_match_table = mmp3_usb_phy_of_match,
> +	},
> +};
> +module_platform_driver(mmp3_usb_phy_driver);
> +
> +MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
> +MODULE_DESCRIPTION("Marvell MMP3 USB PHY Driver");
> +MODULE_LICENSE("GPL v2");
> 

^ permalink raw reply	[flat|nested] 24+ messages in thread

end of thread, back to index

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-30 22:07 [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 01/16] dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 02/16] dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema Lubomir Rintel
2019-09-02 13:39   ` Rob Herring
2019-08-30 22:07 ` [PATCH v3 03/16] dt-bindings: arm: mrvl: Document MMP3 compatible string Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 04/16] dt-bindings: mrvl,intc: Add a MMP3 interrupt controller Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 05/16] dt-bindings: phy-mmp3-usb: Add bindings Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 06/16] ARM: l2c: add definition for FWA in PL310 aux register Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 07/16] ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 08/16] ARM: mmp: map the PGU as well Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 09/16] ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 10/16] ARM: mmp: define MMP_CHIPID by the means of CIU_REG() Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 11/16] ARM: mmp: add support for MMP3 SoC Lubomir Rintel
2019-09-06 23:48   ` Stephen Boyd
2019-08-30 22:07 ` [PATCH v3 12/16] ARM: mmp: add SMP support Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 13/16] ARM: mmp: move cputype.h to include/linux/soc/ Lubomir Rintel
2019-09-02  8:15   ` kbuild test robot
2019-09-05 10:20     ` Arnd Bergmann
2019-08-30 22:07 ` [PATCH v3 14/16] ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h Lubomir Rintel
2019-08-30 22:07 ` [PATCH v3 15/16] phy: phy-mmp3-usb: add a new driver Lubomir Rintel
2019-10-10  8:58   ` Kishon Vijay Abraham I
2019-08-30 22:07 ` [PATCH v3 16/16] ARM: dts: mmp3: Add MMP3 SoC dts file Lubomir Rintel
2019-09-05 10:17   ` Arnd Bergmann
2019-09-05 10:24 ` [PATCH v3 00/16] Initial support for Marvell MMP3 SoC Arnd Bergmann

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