From: Michal Simek <michal.simek@xilinx.com>
To: Michael Tretter <m.tretter@pengutronix.de>,
<linux-arm-kernel@lists.infradead.org>,
<linux-clk@vger.kernel.org>
Cc: <rajanv@xilinx.com>, <tejasp@xilinx.com>, <dshah@xilinx.com>,
<rvisaval@xilinx.com>, <kernel@pengutronix.de>,
<mturquette@baylibre.com>, <sboyd@kernel.org>
Subject: Re: [PATCH v2 09/15] soc: xilinx: vcu: make pll post divider explicit
Date: Thu, 7 Jan 2021 11:01:49 +0100 [thread overview]
Message-ID: <d0c78b40-f5b1-f1d0-ec9c-bfb875be745f@xilinx.com> (raw)
In-Reply-To: <20201221150634.755673-10-m.tretter@pengutronix.de>
On 21. 12. 20 16:06, Michael Tretter wrote:
> According to the downstream driver documentation due to timing
> constraints the output divider of the PLL has to be set to 1/2. Add a
> helper function for that check instead of burying the code in one large
> setup function.
>
> The bit is undocumented and marked as reserved in the register
> reference.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> Changelog:
>
> v2:
> - Use clk_hw instead of name in xvcu_register_pll_post
> ---
> drivers/soc/xilinx/xlnx_vcu.c | 51 ++++++++++++++++++++++++-----------
> 1 file changed, 35 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
> index e38e9c8325a7..6dc58cf58d77 100644
> --- a/drivers/soc/xilinx/xlnx_vcu.c
> +++ b/drivers/soc/xilinx/xlnx_vcu.c
> @@ -81,6 +81,7 @@ struct xvcu_device {
> struct regmap *logicore_reg_ba;
> void __iomem *vcu_slcr_ba;
> struct clk_hw *pll;
> + struct clk_hw *pll_post;
drivers/soc/xilinx/xlnx_vcu.c:86: warning: Function parameter or member
'pll_post' not described in 'xvcu_device'
Thanks,
Michal
next prev parent reply other threads:[~2021-01-07 10:03 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-21 15:06 [PATCH v2 00/15] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter
2020-12-21 15:06 ` [PATCH v2 01/15] ARM: dts: vcu: define indexes for output clocks Michael Tretter
2020-12-21 15:06 ` [PATCH v2 02/15] clk: divider: fix initialization with parent_hw Michael Tretter
2020-12-21 15:06 ` [PATCH v2 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter
2020-12-21 15:06 ` [PATCH v2 04/15] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter
2020-12-21 15:06 ` [PATCH v2 05/15] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter
2020-12-21 15:06 ` [PATCH v2 06/15] soc: xilinx: vcu: implement PLL disable Michael Tretter
2020-12-21 15:06 ` [PATCH v2 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter
2020-12-21 15:06 ` [PATCH v2 08/15] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter
2020-12-21 15:06 ` [PATCH v2 09/15] soc: xilinx: vcu: make pll post divider explicit Michael Tretter
2021-01-07 10:01 ` Michal Simek [this message]
2020-12-21 15:06 ` [PATCH v2 10/15] soc: xilinx: vcu: make the PLL configurable Michael Tretter
2020-12-21 15:06 ` [PATCH v2 11/15] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter
2020-12-21 15:06 ` [PATCH v2 12/15] soc: xilinx: vcu: use bitfields for register definition Michael Tretter
2020-12-21 15:06 ` [PATCH v2 13/15] soc: xilinx: vcu: fix repeated word the in comment Michael Tretter
2020-12-21 15:06 ` [PATCH v2 14/15] soc: xilinx: vcu: fix alignment to open parenthesis Michael Tretter
2020-12-21 15:06 ` [PATCH v2 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Michael Tretter
2021-01-07 10:10 ` [PATCH v2 00/15] soc: xilinx: vcu: Convert driver to clock provider Michal Simek
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