From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F003FC31E5D for ; Tue, 18 Jun 2019 09:19:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C34EF2084B for ; Tue, 18 Jun 2019 09:19:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729176AbfFRJTm (ORCPT ); Tue, 18 Jun 2019 05:19:42 -0400 Received: from foss.arm.com ([217.140.110.172]:58892 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729137AbfFRJTm (ORCPT ); Tue, 18 Jun 2019 05:19:42 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D547E344; Tue, 18 Jun 2019 02:19:40 -0700 (PDT) Received: from [10.1.197.61] (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A18AD3F246; Tue, 18 Jun 2019 02:19:33 -0700 (PDT) Subject: Re: [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during suspend To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> <1560843991-24123-2-git-send-email-skomatineni@nvidia.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1560843991-24123-2-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 18/06/2019 08:46, Sowjanya Komatineni wrote: > Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry > sequence and sc7 entry firmware is run from COP/BPMP-Lite. > > So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence > for Tegra210. > > This patch has fix for leaving the COP IRQ enabled for Tegra210 during > interrupt controller suspend operation. > > Signed-off-by: Sowjanya Komatineni > --- > drivers/irqchip/irq-tegra.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c > index e1f771c72fc4..cf0c07052064 100644 > --- a/drivers/irqchip/irq-tegra.c > +++ b/drivers/irqchip/irq-tegra.c > @@ -44,18 +44,22 @@ static unsigned int num_ictlrs; > > struct tegra_ictlr_soc { > unsigned int num_ictlrs; > + bool supports_sc7; > }; > > static const struct tegra_ictlr_soc tegra20_ictlr_soc = { > .num_ictlrs = 4, > + .supports_sc7 = false, nit: that's the default for a statically initialized structure. > }; > > static const struct tegra_ictlr_soc tegra30_ictlr_soc = { > .num_ictlrs = 5, > + .supports_sc7 = false, > }; > > static const struct tegra_ictlr_soc tegra210_ictlr_soc = { > .num_ictlrs = 6, > + .supports_sc7 = true, > }; > > static const struct of_device_id ictlr_matches[] = { > @@ -67,6 +71,7 @@ static const struct of_device_id ictlr_matches[] = { > > struct tegra_ictlr_info { > void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; > + const struct tegra_ictlr_soc *soc; > #ifdef CONFIG_PM_SLEEP > u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; > u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; > @@ -147,8 +152,19 @@ static int tegra_ictlr_suspend(void) > lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); > lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); > > - /* Disable COP interrupts */ > - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); > + /* > + * AVP/COP/BPMP-Lite is the Tegra boot processor. > + * > + * Tegra210 system suspend flow uses sc7entry firmware which > + * is executed by COP/BPMP and it includes disabling COP IRQ, > + * clamping CPU rail, turning off VDD_CPU, and preparing the > + * system to go to SC7/LP0. > + * > + * COP/BPMP wakes up when COP IRQ is triggered and runs > + * sc7entry-firmware. So need to keep COP interrupt enabled. It is great that you're describing what happens when the system does support this SC7 thing... > + */ > + if (!lic->soc->supports_sc7) > + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); Except that the code actually deals with *not* having this SC7, and you've deleted the one line of comment that was explaining it. > > /* Disable CPU interrupts */ > writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); > @@ -339,6 +355,7 @@ static int __init tegra_ictlr_init(struct device_node *node, > goto out_unmap; > } > > + lic->soc = soc; > tegra_ictlr_syscore_init(); > > pr_info("%pOF: %d interrupts forwarded to %pOF\n", > Otherwise looks OK to me. Thanks, M. -- Jazz is not dead. It just smells funny...