From: <Eugen.Hristev@microchip.com>
To: <sboyd@kernel.org>, <alexandre.belloni@bootlin.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mturquette@baylibre.com>
Cc: <Nicolas.Ferre@microchip.com>
Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date: Tue, 17 Sep 2019 05:59:18 +0000 [thread overview]
Message-ID: <dcae9812-5ae7-567f-0e84-b6166a7f7400@microchip.com> (raw)
In-Reply-To: <20190916195246.CAE5C206C2@mail.kernel.org>
On 16.09.2019 22:52, Stephen Boyd wrote:
> Quoting Eugen.Hristev@microchip.com (2019-09-10 23:39:20)
>> From: Eugen Hristev <eugen.hristev@microchip.com>
>>
>> The PLL input range needs to be able to allow 24 Mhz crystal as input
>> Update the range accordingly in plla characteristics struct
>>
>> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
>> ---
>
> Is there a Fixes: tag for this? Seems like it was always wrong?
>
Hi Stephen,
At the initial design , the 12 Mhz was the only possibility for the
boards themselves. But, with the commit who added this:
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Eugen
next prev parent reply other threads:[~2019-09-17 5:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-11 6:39 [PATCH] clk: at91: allow 24 Mhz clock as input for PLL Eugen.Hristev
2019-09-11 7:03 ` Nicolas.Ferre
2019-09-12 11:06 ` Alexander Dahl
2019-09-12 11:28 ` Eugen.Hristev
2019-09-16 19:52 ` Stephen Boyd
2019-09-17 5:59 ` Eugen.Hristev [this message]
2019-09-18 5:00 ` Stephen Boyd
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