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From: Manu Gautam <mgautam@codeaurora.org>
To: Stephen Boyd <sboyd@kernel.org>,
	Marc Gonzalez <marc.w.gonzalez@free.fr>,
	Michael Turquette <mturquette@baylibre.com>
Cc: Jeffrey Hugo <jhugo@codeaurora.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	MSM <linux-arm-msm@vger.kernel.org>,
	Evan Green <evgreen@chromium.org>,
	Douglas Anderson <dianders@chromium.org>,
	Vinod Koul <vkoul@kernel.org>,
	Amit Nischal <anischal@codeaurora.org>
Subject: Re: [PATCH v1] clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998
Date: Fri, 11 Oct 2019 09:17:12 +0530
Message-ID: <df6cae85-f5f6-cd93-0dd3-17f0f28fe376@codeaurora.org> (raw)
In-Reply-To: <20191010194810.47D062067B@mail.kernel.org>


On 10/11/2019 1:18 AM, Stephen Boyd wrote:
> Quoting Manu Gautam (2019-10-10 00:33:32)
>> Hi,
>>
>> On 10/10/2019 9:45 AM, Stephen Boyd wrote:
>>> Quoting Manu Gautam (2019-10-09 01:31:09)
>> [snip]
>>>> I have followed this up with QMP PHY hardware designers and they have
>>>> confirmed that QMP PHY must have pipe clock enabled at the beginning
>>>> of initialization sequence i.e. before bringing it out of reset and starting it.
>>> Awesome, thanks for following up.
>>>
>>>> Otherwise there is possibility of incorrect locking of pipe_interface/
>>>> retime buffers in PHY.
>>>> Hence, for both USB and PCIe we have to continue to use HALT_SKIP flag.
>>> Does anything go wrong if we just leave these clks enabled forever out
>>> of boot? I'm inclined to rip the clks out and just slam the branch
>>> enable bit on all the time in gcc driver probe and return NULL to the
>>> callers of clk_get() for these clks. I don't see how this would be a
>>> problem because when the upstream phy is disabled this clk is disabled
>>> and so we aren't wasting power. It should also save us time and memory
>>> because now we don't have to call into the clk framework to turn it on
>>> and sequence that just right in the phy driver.
>> That might work, however on some platforms gcc_pipe_clk parent is changed to
>> XO and back to phy_pipe_clk across low power mode.
>> It requires PHY driver to use clk_set_parent().
>>
> Hm ok. Where is the call to clk_set_parent()? I don't see this in the
> kernel.
>
>  $ git grep clk_set_parent -- drivers/usb/phy drivers/phy | wc -l
>  0
>
> What platforms do this? Are they upstream?

They are some recent platforms and not on upstream yet.

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


  reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25 13:49 Marc Gonzalez
2019-03-28 16:26 ` Marc Gonzalez
2019-03-29 22:32   ` Stephen Boyd
2019-04-01  8:48     ` Marc Gonzalez
2019-10-09  8:31     ` Manu Gautam
2019-10-10  4:15       ` Stephen Boyd
2019-10-10  7:33         ` Manu Gautam
2019-10-10 19:48           ` Stephen Boyd
2019-10-11  3:47             ` Manu Gautam [this message]
2019-10-17 17:49               ` Stephen Boyd
2019-04-05 12:29 ` Marc Gonzalez
2019-04-09 13:25 ` Jeffrey Hugo
2019-04-11 20:38 ` Stephen Boyd

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