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Subject: Re: [RFC PATCH v5 6/9] media: tegra: Add Tegra210 Video input driver
From:   Sowjanya Komatineni <skomatineni@nvidia.com>
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
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On 3/24/20 6:08 PM, Sowjanya Komatineni wrote:
>
> On 3/24/20 5:34 PM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 23.03.2020 20:52, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>>> +static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan)
>>> +{
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 /* disable clock gating to enable continuous =
clock */
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, 0)=
;
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 /*
>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Soft reset memory client interface, p=
ixel format logic, sensor
>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * control logic, and a shadow copy logi=
c to bring VI to clean=20
>>> state.
>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0xf=
);
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 usleep_range(100, 200);
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0x0=
);
>> Is it safe to reset MCCIF without blocking and flushing memory requests
>> at first?
> Yes to bring VI to clean state on errors its recommended by HW design=20
> team.
BTW, just to be clear this is Software reset.