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[94.29.39.224]) by smtp.googlemail.com with ESMTPSA id r23sm7375579lfe.53.2020.03.10.10.50.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Mar 2020 10:50:08 -0700 (PDT) Subject: Re: [PATCH v5 1/8] clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 To: Thierry Reding Cc: Jon Hunter , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Joseph Lo , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20200310152003.2945170-1-thierry.reding@gmail.com> <20200310152003.2945170-2-thierry.reding@gmail.com> <9b343fd1-15df-409a-390f-e30fa6bbbfe7@gmail.com> <20200310170508.GA3079591@ulmo> From: Dmitry Osipenko Message-ID: Date: Tue, 10 Mar 2020 20:50:07 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200310170508.GA3079591@ulmo> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org 10.03.2020 20:05, Thierry Reding пишет: > On Tue, Mar 10, 2020 at 07:19:59PM +0300, Dmitry Osipenko wrote: >> 10.03.2020 18:19, Thierry Reding пишет: >>> From: Joseph Lo >>> >>> Introduce the low jitter path of PLLP and PLLMB which can be used as EMC >>> clock source. >>> >>> Signed-off-by: Joseph Lo >>> Signed-off-by: Thierry Reding >>> --- >>> drivers/clk/tegra/clk-tegra210.c | 11 +++++++++++ >>> include/dt-bindings/clock/tegra210-car.h | 4 ++-- >>> 2 files changed, 13 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c >>> index 45d54ead30bc..f99647b4a71f 100644 >>> --- a/drivers/clk/tegra/clk-tegra210.c >>> +++ b/drivers/clk/tegra/clk-tegra210.c >>> @@ -3161,6 +3161,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base, >>> clk_register_clkdev(clk, "pll_m_ud", NULL); >>> clks[TEGRA210_CLK_PLL_M_UD] = clk; >>> >>> + /* PLLMB_UD */ >>> + clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", >>> + CLK_SET_RATE_PARENT, 1, 1); >>> + clk_register_clkdev(clk, "pll_mb_ud", NULL); >>> + clks[TEGRA210_CLK_PLL_MB_UD] = clk; >>> + >>> + /* PLLP_UD */ >>> + clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", >>> + 0, 1, 1); >>> + clks[TEGRA210_CLK_PLL_P_UD] = clk; >> >> Isn't it possible to auto-enable the low-jitter bit when necessary >> during of the rate-change based on a given clock-rate? > > I don't think so. These new clocks (pll_mb_ud and pll_p_ud) are parents > for the emc clock, so they are needed to properly reflect the position > of the emc clock in the clock tree. Okay, even if it's possible to do, I guess that won't be very compatible with the firmware.