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David Alan Gilbert" , , , Subject: Re: [PATCH v7 01/45] x86/compressed/64: detect/setup SEV/SME features earlier in boot Message-ID: <20211112203001.kdzhpgp3uqcr2dy5@amd.com> References: <20211110220731.2396491-1-brijesh.singh@amd.com> <20211110220731.2396491-2-brijesh.singh@amd.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9e0d02b3-6906-4750-1800-08d9a61b41b6 X-MS-TrafficTypeDiagnostic: DM6PR12MB3162: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: l6Vs41jjXNa8fdImwJcDfz+L77M6wmTAHmeaN8fFttbYE9jvfQPC96bYAaf0uSrz6OE2zmfrqiPLl/R4xdCLST0aVaCplj0jokyIoMS6w7oQH7NmnJUV7yUAcNWAd4I4LWseB2X6U95r+jma0lFMXYHHvOu3YN4p449F2Vy2fP3VF2w70EMzp9M0IRI1Vg7jYWcRwqxK3TVsMnm0zBIcLRlyc+NIgL7CHLJsgNZsLT2g0CVg4Ge3bpEC2Z2NcZGR+Kgw3U6huvx/wbFAzVx5DtMQ4PTvMqtnSKJsvAqh/bOny8GngwUkiiXyQBMFO7BqTK234i72qgQPi2lHO+pPp3chdYDvmTP5RS8as000YpbfCVEq5EFKpDx6aG56u8ftlJsinkDRyeCNEmN1GPprtd9f82y/sKmb/PyMGKsrSgTKBJH9pH04S41ULHWxtp5Jvvd/zqWrGXyOFufXJ7zNcaYmYwgMQXot9GuamcvN5jwX7Bja/axAKn0/W6XoSNFsC95xoJu/kbp6PgKx6UhsN2Rn0dqbfJG93yq6cWosT0KlQ7ZDi5KLKKMPCB0VYCow/TDvXbdT+bvi/yBkX3iJXr9DHWeLuGMw4X6Yt1L7roipP3Hn30GeovRKy8uUYdYLKcdjiCGEbZ+2gMwzQsMoa98l+8eW02xxVwp0fZxAc1sbeMU7pG6xUynmmG0TG4gEmXL4/2XOU0bpPuy3EF2fepzWPal70oDJ9tsTbC04QRJe/VlA9fo3UiLGARwv0gqsAawyRiACRJZClRQS5+Ble6pru1I45V6Q53OiyY3d8s0E5/KT6XMrLpB1d7cmEUO+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(336012)(8936002)(86362001)(54906003)(8676002)(2906002)(44832011)(316002)(426003)(1076003)(81166007)(6916009)(6666004)(70206006)(83380400001)(82310400003)(5660300002)(7416002)(356005)(2616005)(4326008)(508600001)(7406005)(26005)(36756003)(186003)(47076005)(16526019)(45080400002)(36860700001)(70586007)(966005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2021 20:30:24.5966 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e0d02b3-6906-4750-1800-08d9a61b41b6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3162 On Fri, Nov 12, 2021 at 05:52:51PM +0100, Borislav Petkov wrote: > On Wed, Nov 10, 2021 at 04:06:47PM -0600, Brijesh Singh wrote: > > +void sev_enable(struct boot_params *bp) > > +{ > > + unsigned int eax, ebx, ecx, edx; > > + > > + /* Check for the SME/SEV support leaf */ > > + eax = 0x80000000; > > + ecx = 0; > > + native_cpuid(&eax, &ebx, &ecx, &edx); > > + if (eax < 0x8000001f) > > + return; > > + > > + /* > > + * Check for the SME/SEV feature: > > + * CPUID Fn8000_001F[EAX] > > + * - Bit 0 - Secure Memory Encryption support > > + * - Bit 1 - Secure Encrypted Virtualization support > > + * CPUID Fn8000_001F[EBX] > > + * - Bits 5:0 - Pagetable bit position used to indicate encryption > > + */ > > + eax = 0x8000001f; > > + ecx = 0; > > + native_cpuid(&eax, &ebx, &ecx, &edx); > > + /* Check whether SEV is supported */ > > + if (!(eax & BIT(1))) > > + return; > > + > > + /* Check the SEV MSR whether SEV or SME is enabled */ > > + sev_status = rd_sev_status_msr(); > > + > > + if (!(sev_status & MSR_AMD64_SEV_ENABLED)) > > + error("SEV support indicated by CPUID, but not SEV status MSR."); > > What is the practical purpose of this test? In the current QEMU/KVM implementation the SEV* CPUID bits are only exposed for SEV guests, so this was more of a sanity check on that. But looking at things more closely: that's more of a VMM-specific behavior and isn't necessarily an invalid guest configuration as far as the spec is concerned, so I think this check should be dropped. > > > + sme_me_mask = 1UL << (ebx & 0x3f); > > sme_me_mask = BIT_ULL(ebx & 0x3f); Will do. Thanks, Mike > > Thx. > > -- > Regards/Gruss, > Boris. > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeople.kernel.org%2Ftglx%2Fnotes-about-netiquette&data=04%7C01%7Cmichael.roth%40amd.com%7Ca6bf3479fffa4b5eee8b08d9a5fce2e2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637723327924654730%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=SRy8YSe8a2njNc6IT8CGKv0hUefSOW55DJV%2Fi2Lhkic%3D&reserved=0