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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT005.mail.protection.outlook.com (100.127.140.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6043.25 via Frontend Transport; Fri, 27 Jan 2023 11:42:02 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Fri, 27 Jan 2023 11:42:01 +0000 Received: from e124191.cambridge.arm.com (10.1.197.45) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Fri, 27 Jan 2023 11:41:55 +0000 From: Joey Gouly To: Andrew Jones , , CC: , Alexandru Elisei , Christoffer Dall , Fuad Tabba , Jean-Philippe Brucker , Joey Gouly , Marc Zyngier , Mark Rutland , Oliver Upton , Paolo Bonzini , Quentin Perret , Steven Price , Suzuki K Poulose , "Thomas Huth" , Will Deacon , Zenghui Yu , , , , Subject: [RFC kvm-unit-tests 08/27] arm: realm: Realm initialisation Date: Fri, 27 Jan 2023 11:40:49 +0000 Message-ID: <20230127114108.10025-9-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230127114108.10025-1-joey.gouly@arm.com> References: <20230127112248.136810-1-suzuki.poulose@arm.com> <20230127114108.10025-1-joey.gouly@arm.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT005:EE_|VE1PR08MB5583:EE_|AM7EUR03FT020:EE_|AS2PR08MB9894:EE_ X-MS-Office365-Filtering-Correlation-Id: e0977e95-b5e7-4c57-2743-08db005b8875 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 11:42:13.3522 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0977e95-b5e7-4c57-2743-08db005b8875 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9894 During the boot, run a check for the presence of RMM. If we are Realm, detect the Realm configuration using RSI and initialise the key parameters. Also expose a helper to indicate if this is running inside a Realm Co-developed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Signed-off-by: Joey Gouly --- arm/Makefile.arm64 | 1 + lib/arm/asm/rsi.h | 16 ++++++++++ lib/arm/setup.c | 3 ++ lib/arm64/asm/processor.h | 8 +++++ lib/arm64/asm/rsi.h | 36 +++++++++++++++++++++ lib/arm64/rsi.c | 67 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 131 insertions(+) create mode 100644 lib/arm/asm/rsi.h create mode 100644 lib/arm64/asm/rsi.h create mode 100644 lib/arm64/rsi.c diff --git a/arm/Makefile.arm64 b/arm/Makefile.arm64 index 42e18e77..ab557f84 100644 --- a/arm/Makefile.arm64 +++ b/arm/Makefile.arm64 @@ -24,6 +24,7 @@ cstart.o = $(TEST_DIR)/cstart64.o cflatobjs += lib/arm64/processor.o cflatobjs += lib/arm64/spinlock.o cflatobjs += lib/arm64/gic-v3-its.o lib/arm64/gic-v3-its-cmd.o +cflatobjs += lib/arm64/rsi.o OBJDIRS += lib/arm64 diff --git a/lib/arm/asm/rsi.h b/lib/arm/asm/rsi.h new file mode 100644 index 00000000..d1f72c25 --- /dev/null +++ b/lib/arm/asm/rsi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Arm Limited. + * All rights reserved. + */ +#ifndef __ASMARM_RSI_H_ +#define __ASMARM_RSI_H_ + +#include + +static inline bool is_realm(void) +{ + return false; +} + +#endif /* __ASMARM_RSI_H_ */ diff --git a/lib/arm/setup.c b/lib/arm/setup.c index 65d98e97..36d4d826 100644 --- a/lib/arm/setup.c +++ b/lib/arm/setup.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -244,6 +245,8 @@ void setup(const void *fdt, phys_addr_t freemem_start) u32 fdt_size; int ret; + arm_rsi_init(); + assert(sizeof(long) == 8 || freemem_start < (3ul << 30)); freemem = (void *)(unsigned long)freemem_start; diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h index 1c73ba32..320ebaef 100644 --- a/lib/arm64/asm/processor.h +++ b/lib/arm64/asm/processor.h @@ -114,6 +114,14 @@ static inline unsigned long get_id_aa64mmfr0_el1(void) #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 +static inline unsigned long get_id_aa64pfr0_el1(void) +{ + return read_sysreg(id_aa64pfr0_el1); +} + +#define ID_AA64PFR0_EL1_EL3 (0xf << 12) +#define ID_AA64PFR0_EL1_EL3_NI (0x0 << 12) + static inline bool system_supports_granule(size_t granule) { u32 shift; diff --git a/lib/arm64/asm/rsi.h b/lib/arm64/asm/rsi.h new file mode 100644 index 00000000..8b9b91b2 --- /dev/null +++ b/lib/arm64/asm/rsi.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Arm Limited. + * All rights reserved. + */ +#ifndef __ASMARM64_RSI_H_ +#define __ASMARM64_RSI_H_ + +#include + +#include +#include +#include + +#define RSI_GRANULE_SIZE SZ_4K + +extern bool rsi_present; + +void arm_rsi_init(void); + +int rsi_invoke(unsigned int function_id, unsigned long arg0, + unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4, + unsigned long arg5, unsigned long arg6, + unsigned long arg7, unsigned long arg8, + unsigned long arg9, unsigned long arg10, + struct smccc_result *result); + +int rsi_get_version(void); + +static inline bool is_realm(void) +{ + return rsi_present; +} + +#endif /* __ASMARM64_RSI_H_ */ diff --git a/lib/arm64/rsi.c b/lib/arm64/rsi.c new file mode 100644 index 00000000..23a4e963 --- /dev/null +++ b/lib/arm64/rsi.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Arm Limited. + * All rights reserved. + */ +#include + +#include +#include +#include + +bool rsi_present; + +int rsi_invoke(unsigned int function_id, unsigned long arg0, + unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4, + unsigned long arg5, unsigned long arg6, + unsigned long arg7, unsigned long arg8, + unsigned long arg9, unsigned long arg10, + struct smccc_result *result) +{ + return arm_smccc_smc(function_id, arg0, arg1, arg2, arg3, arg4, arg5, + arg6, arg7, arg8, arg9, arg10, result); +} + +struct rsi_realm_config __attribute__((aligned(RSI_GRANULE_SIZE))) config; + +static unsigned long rsi_get_realm_config(struct rsi_realm_config *cfg) +{ + struct smccc_result res; + + rsi_invoke(SMC_RSI_REALM_CONFIG, __virt_to_phys((unsigned long)cfg), + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &res); + + return res.r0; +} + +int rsi_get_version(void) +{ + struct smccc_result res = {}; + int ret; + + if ((get_id_aa64pfr0_el1() & ID_AA64PFR0_EL1_EL3) == ID_AA64PFR0_EL1_EL3_NI) + return -1; + + ret = rsi_invoke(SMC_RSI_ABI_VERSION, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + &res); + if (ret) + return ret; + + return res.r0; +} + +void arm_rsi_init(void) +{ + if (rsi_get_version() != RSI_ABI_VERSION) + return; + + if (rsi_get_realm_config(&config)) + return; + + rsi_present = true; + + phys_mask_shift = (config.ipa_width - 1); + /* Set the upper bit of the IPA as the NS_SHARED pte attribute */ + prot_ns_shared = (1UL << phys_mask_shift); +} -- 2.17.1