From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.skyhub.de (unknown [5.9.137.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C49AF2C80 for ; Thu, 21 Oct 2021 18:46:47 +0000 (UTC) Received: from zn.tnic (p200300ec2f1912005c22c248f35985a5.dip0.t-ipconnect.de [IPv6:2003:ec:2f19:1200:5c22:c248:f359:85a5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id DF4681EC053B; Thu, 21 Oct 2021 20:46:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1634841992; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=WvxWgq2dLAGqen8UM31jjC2Q8Nfg2PZVc4rOcpkz+RQ=; b=TabvkIr+qmtR55/vwHcln6Rs8ye3YUSx9Dog/d2cXtpz1H4TnQNoL9czyC7cFT+ujxLj0B cZfWEH+Var/MpHaA0blwxefl9GWCYta5nWH3/guDkDjWtCVLZpnZukGu/mc4DX54BQoph+ yDf69FlEAUe5W1ly8gCa/HifIYG1APE= Date: Thu, 21 Oct 2021 20:46:30 +0200 From: Borislav Petkov To: "Dr. David Alan Gilbert" Cc: Michael Roth , Brijesh Singh , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH v6 08/42] x86/sev-es: initialize sev_status/features within #VC handler Message-ID: References: <20211018184003.3ob2uxcpd2rpee3s@amd.com> <20211020161023.hzbj53ehmzjrt4xd@amd.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: On Thu, Oct 21, 2021 at 06:47:50PM +0100, Dr. David Alan Gilbert wrote: > Hang on, I think it's perfectly fine for it to clear that bit - it just > gets caught if it *sets* it (i.e. claims to be a chip unaffected by the > bug). > > i.e. if guestval=0 then (GustVal & whatever) == GuestVal > fine > > ? Bah, ofc. The name of the bit is NullSelectorClearsBase - so when it is clear, we will note we're affected, as that patch does: + /* + * CPUID bit above wasn't set. If this kernel is still running + * as a HV guest, then the HV has decided not to advertize + * that CPUID bit for whatever reason. For example, one + * member of the migration pool might be vulnerable. Which + * means, the bug is present: set the BUG flag and return. + */ + if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { + set_cpu_bug(c, X86_BUG_NULL_SEG); + return; + } I have managed to flip the meaning in my mind. Ok, that makes more sense. Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette