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[82.30.61.225]) by smtp.gmail.com with ESMTPSA id l40sm6144308wms.31.2021.10.21.10.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 10:47:52 -0700 (PDT) Date: Thu, 21 Oct 2021 18:47:50 +0100 From: "Dr. David Alan Gilbert" To: Borislav Petkov Cc: Michael Roth , Brijesh Singh , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH v6 08/42] x86/sev-es: initialize sev_status/features within #VC handler Message-ID: References: <20211008180453.462291-9-brijesh.singh@amd.com> <20211018184003.3ob2uxcpd2rpee3s@amd.com> <20211020161023.hzbj53ehmzjrt4xd@amd.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/2.0.7 (2021-05-04) Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline * Borislav Petkov (bp@alien8.de) wrote: > On Thu, Oct 21, 2021 at 06:12:53PM +0100, Dr. David Alan Gilbert wrote: > > OK, so that bit is 8...21 Eax ext2eax bit 6 page 1-109 > > > > then 2.1.5.3 CPUID policy enforcement shows 8...21 EAX as > > 'bitmask' > > 'bits set in the GuestVal must also be set in HostVal. > > This is often applied to feature fields where each bit indicates > > support for a feature' > > > > So that's right isn't it? > > Yap, AFAIRC, it would fail the check if: > > (GuestVal & HostVal) != GuestVal > > and GuestVal is "the CPUID result value created by the hypervisor that > it wants to give to the guest". Let's say it clears bit 6 there. ^^^^^^^ > Then HostVal comes in which is "the actual CPUID result value specified > in this PPR" and there the guest catches the HV lying its *ss off. > > :-) Hang on, I think it's perfectly fine for it to clear that bit - it just gets caught if it *sets* it (i.e. claims to be a chip unaffected by the bug). i.e. if guestval=0 then (GustVal & whatever) == GuestVal fine ? Dave > > -- > Regards/Gruss, > Boris. > > https://people.kernel.org/tglx/notes-about-netiquette > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK