From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.skyhub.de (mail.skyhub.de [5.9.137.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D7EA2C85 for ; Thu, 4 Nov 2021 14:07:09 +0000 (UTC) Received: from zn.tnic (p200300ec2f0f2b00292987ac0c06fcda.dip0.t-ipconnect.de [IPv6:2003:ec:2f0f:2b00:2929:87ac:c06:fcda]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 07B031EC0570; Thu, 4 Nov 2021 14:59:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1636034341; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=7LX03mAYK04otWZOoY71ALabwci0dk1MWKslK4zWu2I=; b=KR+lLKKLVG+OimGX0G+TVfeAzPp3+DAiK71o99+TN8MKguX6+YMASSnyMiA33sWx6z9RXk PtVWl2Hv+ntT4D5AF+ZUH0n29RNRaoDCwwzmVLEOIeXtzSFlfK82CoRS/vUfvkp7K/I00A cmZCFAiEROjuNQ7+z/kvpv4vyBBOcTY= Date: Thu, 4 Nov 2021 14:58:49 +0100 From: Borislav Petkov To: Brijesh Singh Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH v6 14/42] x86/sev: Register GHCB memory when SEV-SNP is active Message-ID: References: <20211008180453.462291-1-brijesh.singh@amd.com> <20211008180453.462291-15-brijesh.singh@amd.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: On Wed, Nov 03, 2021 at 03:10:16PM -0500, Brijesh Singh wrote: > Looking at the secondary CPU bring up path it seems that we will not be > getting #VC until the early_setup_idt() is called. I am thinking to add > function to register the GHCB from the early_setup_idt() > > early_setup_idt() > { > ... > if (IS_ENABLED(CONFIG_MEM_ENCRYPT)) > sev_snp_register_ghcb() > ... > } > > The above will cover the APs That will cover the APs during early boot as that is being called from asm. > and for BSP case I can call the same function just after the final IDT > is loaded Why after and not before? > cpu_init_exception_handling() > { > ... > ... > /* Finally load the IDT */ > load_current_idt(); > > if (IS_ENABLED(CONFIG_MEM_ENCRYPT)) > sev_snp_register_ghcb() > > } That is also called on the APs - not only the BSP. trap_init() calls it from start_kernel() which is the BSP and cpu_init_secondary() calls it too, which is ofc the APs. I guess that should be ok since you're calling the same function from both but WTH do I know... -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette