From: Corentin Labbe <clabbe@baylibre.com>
To: davem@davemloft.net, herbert@gondor.apana.org.au,
mripard@kernel.org, wens@csie.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org,
Corentin Labbe <clabbe@baylibre.com>
Subject: [PATCH v4 10/17] crypto: sun8i-ce: handle different error registers
Date: Tue, 21 Jul 2020 19:06:24 +0000 [thread overview]
Message-ID: <1595358391-34525-11-git-send-email-clabbe@baylibre.com> (raw)
In-Reply-To: <1595358391-34525-1-git-send-email-clabbe@baylibre.com>
Error registers are different across SoCs.
This patch handle those difference.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
.../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 62 ++++++++++++++++---
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 8 +++
2 files changed, 62 insertions(+), 8 deletions(-)
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
index 0b47a51e1cfc..4cc98180be3f 100644
--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
@@ -40,7 +40,8 @@ static const struct ce_variant ce_h3_variant = {
.ce_clks = {
{ "bus", 0, 200000000 },
{ "mod", 50000000, 0 },
- }
+ },
+ .esr = ESR_H3,
};
static const struct ce_variant ce_h5_variant = {
@@ -51,7 +52,8 @@ static const struct ce_variant ce_h5_variant = {
.ce_clks = {
{ "bus", 0, 200000000 },
{ "mod", 300000000, 0 },
- }
+ },
+ .esr = ESR_H5,
};
static const struct ce_variant ce_h6_variant = {
@@ -64,7 +66,8 @@ static const struct ce_variant ce_h6_variant = {
{ "bus", 0, 200000000 },
{ "mod", 300000000, 0 },
{ "ram", 0, 400000000 },
- }
+ },
+ .esr = ESR_H6,
};
static const struct ce_variant ce_a64_variant = {
@@ -75,7 +78,8 @@ static const struct ce_variant ce_a64_variant = {
.ce_clks = {
{ "bus", 0, 200000000 },
{ "mod", 300000000, 0 },
- }
+ },
+ .esr = ESR_A64,
};
static const struct ce_variant ce_r40_variant = {
@@ -86,7 +90,8 @@ static const struct ce_variant ce_r40_variant = {
.ce_clks = {
{ "bus", 0, 200000000 },
{ "mod", 300000000, 0 },
- }
+ },
+ .esr = ESR_R40,
};
/*
@@ -102,6 +107,7 @@ int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name)
{
u32 v;
int err = 0;
+ struct ce_task *cet = ce->chanlist[flow].tl;
#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
ce->chanlist[flow].stat_req++;
@@ -131,19 +137,56 @@ int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name)
msecs_to_jiffies(ce->chanlist[flow].timeout));
if (ce->chanlist[flow].status == 0) {
- dev_err(ce->dev, "DMA timeout for %s\n", name);
+ dev_err(ce->dev, "DMA timeout for %s (tm=%d) on flow %d\n", name,
+ ce->chanlist[flow].timeout, flow);
err = -EFAULT;
}
/* No need to lock for this read, the channel is locked so
* nothing could modify the error value for this channel
*/
v = readl(ce->base + CE_ESR);
- if (v) {
+ switch (ce->variant->esr) {
+ case ESR_H3:
+ /* Sadly, the error bit is not per flow */
+ if (v) {
+ dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
+ err = -EFAULT;
+ print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4,
+ cet, sizeof(struct ce_task), false);
+ }
+ if (v & CE_ERR_ALGO_NOTSUP)
+ dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
+ if (v & CE_ERR_DATALEN)
+ dev_err(ce->dev, "CE ERROR: data length error\n");
+ if (v & CE_ERR_KEYSRAM)
+ dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
+ break;
+ case ESR_A64:
+ case ESR_H5:
+ case ESR_R40:
v >>= (flow * 4);
+ v &= 0xF;
+ if (v) {
+ dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
+ err = -EFAULT;
+ print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4,
+ cet, sizeof(struct ce_task), false);
+ }
+ if (v & CE_ERR_ALGO_NOTSUP)
+ dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
+ if (v & CE_ERR_DATALEN)
+ dev_err(ce->dev, "CE ERROR: data length error\n");
+ if (v & CE_ERR_KEYSRAM)
+ dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
+ break;
+ case ESR_H6:
+ v >>= (flow * 8);
v &= 0xFF;
if (v) {
dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
err = -EFAULT;
+ print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4,
+ cet, sizeof(struct ce_task), false);
}
if (v & CE_ERR_ALGO_NOTSUP)
dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
@@ -153,7 +196,10 @@ int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name)
dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
if (v & CE_ERR_ADDR_INVALID)
dev_err(ce->dev, "CE ERROR: address invalid\n");
- }
+ if (v & CE_ERR_KEYLADDER)
+ dev_err(ce->dev, "CE ERROR: key ladder configuration error\n");
+ break;
+ }
return err;
}
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
index 084a962b8d4f..eea0847dc1e8 100644
--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
@@ -65,6 +65,12 @@
#define CE_ERR_ADDR_INVALID BIT(5)
#define CE_ERR_KEYLADDER BIT(6)
+#define ESR_H3 0
+#define ESR_A64 1
+#define ESR_R40 2
+#define ESR_H5 3
+#define ESR_H6 4
+
#define CE_DIE_ID_SHIFT 16
#define CE_DIE_ID_MASK 0x07
@@ -94,12 +100,14 @@ struct ce_clock {
* @has_t_dlen_in_bytes: Does the request size for cipher is in
* bytes or words
* @ce_clks: list of clocks needed by this variant
+ * @esr: The type of error register
*/
struct ce_variant {
char alg_cipher[CE_ID_CIPHER_MAX];
u32 op_mode[CE_ID_OP_MAX];
bool has_t_dlen_in_bytes;
struct ce_clock ce_clks[CE_MAX_CLOCKS];
+ int esr;
};
struct sginfo {
--
2.26.2
next prev parent reply other threads:[~2020-07-21 19:07 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-21 19:06 [PATCH v4 00/17] crypto: allwinner: add xRNG and hashes Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 01/17] crypto: sun8i-ss: Add SS_START define Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 02/17] crypto: sun8i-ss: Add support for the PRNG Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 03/17] crypto: sun8i-ss: support hash algorithms Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 04/17] crypto: sun8i-ss: fix a trivial typo Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 05/17] crypto: sun8i-ss: Add more comment on some structures Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 06/17] crypto: sun8i-ss: better debug printing Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 07/17] crypto: sun8i-ce: handle endianness of t_common_ctl Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 08/17] crypto: sun8i-ce: move iv data to request context Corentin Labbe
2020-07-31 8:24 ` Herbert Xu
2020-08-21 7:35 ` LABBE Corentin
2020-08-21 7:36 ` Herbert Xu
2020-07-21 19:06 ` [PATCH v4 09/17] crypto: sun8i-ce: split into prepare/run/unprepare Corentin Labbe
2020-07-21 19:06 ` Corentin Labbe [this message]
2020-07-21 19:06 ` [PATCH v4 11/17] crypto: sun8i-ce: rename has_t_dlen_in_bytes to cipher_t_dlen_in_bytes Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 12/17] crypto: sun8i-ce: support hash algorithms Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 13/17] crypto: sun8i-ce: Add stat_bytes debugfs Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 14/17] crypto: sun8i-ce: Add support for the PRNG Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 15/17] crypto: sun8i-ce: Add support for the TRNG Corentin Labbe
2020-07-21 19:06 ` [PATCH v4 16/17] crypto: sun8i-ce: fix comparison of integer expressions of different signedness Corentin Labbe
2020-07-21 21:32 ` Joe Perches
2020-07-22 4:57 ` [PATCH] Makefile.extrawarn: Move sign-compare from W=2 to W=3 Joe Perches
2020-07-27 4:55 ` Masahiro Yamada
2020-07-22 6:21 ` [PATCH v4 16/17] crypto: sun8i-ce: fix comparison of integer expressions of different signedness LABBE Corentin
2020-07-21 19:06 ` [PATCH v4 17/17] crypto: sun8i-ss: " Corentin Labbe
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