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[67.185.54.80]) by smtp.gmail.com with ESMTPSA id h1sm22730534pfg.55.2019.07.15.13.19.48 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 15 Jul 2019 13:19:48 -0700 (PDT) From: Andrey Smirnov To: linux-crypto@vger.kernel.org Cc: Andrey Smirnov , Chris Spencer , Cory Tusar , Chris Healy , Lucas Stach , =?UTF-8?q?Horia=20Geant=C4=83?= , Aymen Sghaier , Leonard Crestez , linux-kernel@vger.kernel.org Subject: [PATCH v5 00/14] crypto: caam - Add i.MX8MQ support Date: Mon, 15 Jul 2019 13:19:28 -0700 Message-Id: <20190715201942.17309-1-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Everyone: Picking up where Chris left off (I chatted with him privately beforehead), this series adds support for i.MX8MQ to CAAM driver. Just like [v1], this series is i.MX8MQ only. Feedback is welcome! Thanks, Andrey Smirnov Changes since [v4]: - Fixed missing sentinel element in "crypto: caam - simplfy clock initialization" - Squashed all of the devers related patches into a single one and converted IRQ allocation to use devres while at it - Added "crypto: caam - request JR IRQ as the last step" as discussed Changes since [v3]: - Patchset changed to select DMA size at runtime in order to enable support for both i.MX8MQ and Layerscape at the same time. I only tested the patches on i.MX6,7 and 8MQ, since I don't have access to any of the Layerscape HW. Any help in that regard would be appareciated. - Bulk clocks and their number are now stored as a part of struct caam_drv_private to simplify allocation and cleanup code (no special context needed) - Renamed 'soc_attr' -> 'imx_soc_match' for clarity Changes since [v2]: - Dropped "crypto: caam - do not initialise clocks on the i.MX8" and replaced it with "crypto: caam - simplfy clock initialization" and "crypto: caam - add clock entry for i.MX8MQ" Changes since [v1] - Series reworked to continue using register based interface for queueing RNG initialization job, dropping "crypto: caam - use job ring for RNG instantiation instead of DECO" - Added a patch to share DMA mask selection code - Added missing Signed-off-by for authors of original NXP tree commits that this sereis is based on [v4] lore.kernel.org/r/20190703081327.17505-1-andrew.smirnov@gmail.com [v3] lore.kernel.org/r/20190617160339.29179-1-andrew.smirnov@gmail.com [v2] lore.kernel.org/r/20190607200225.21419-1-andrew.smirnov@gmail.com [v1] https://patchwork.kernel.org/cover/10825625/ Andrey Smirnov (14): crypto: caam - move DMA mask selection into a function crypto: caam - simplfy clock initialization crypto: caam - convert caam_jr_init() to use devres crypto: caam - request JR IRQ as the last step crytpo: caam - make use of iowrite64*_hi_lo in wr_reg64 crypto: caam - use ioread64*_hi_lo in rd_reg64 crypto: caam - drop 64-bit only wr/rd_reg64() crypto: caam - make CAAM_PTR_SZ dynamic crypto: caam - move cpu_to_caam_dma() selection to runtime crypto: caam - drop explicit usage of struct jr_outentry crypto: caam - don't hardcode inpentry size crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs crypto: caam - always select job ring via RSR on i.MX8MQ crypto: caam - add clock entry for i.MX8MQ drivers/crypto/caam/caamalg.c | 2 +- drivers/crypto/caam/caamhash.c | 2 +- drivers/crypto/caam/caampkc.c | 8 +- drivers/crypto/caam/caamrng.c | 2 +- drivers/crypto/caam/ctrl.c | 225 ++++++++++++++---------------- drivers/crypto/caam/desc_constr.h | 20 ++- drivers/crypto/caam/error.c | 3 + drivers/crypto/caam/intern.h | 32 ++++- drivers/crypto/caam/jr.c | 95 ++++--------- drivers/crypto/caam/pdb.h | 16 ++- drivers/crypto/caam/pkc_desc.c | 8 +- drivers/crypto/caam/regs.h | 139 ++++++++++++------ 12 files changed, 306 insertions(+), 246 deletions(-) -- 2.21.0