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[86.9.19.6]) by smtp.gmail.com with ESMTPSA id s1sm4927621wrg.80.2019.08.29.03.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 03:49:44 -0700 (PDT) Date: Thu, 29 Aug 2019 11:49:42 +0100 From: Daniel Thompson To: Tomer Maimon Cc: mpm@selenic.com, herbert@gondor.apana.org.au, arnd@arndb.de, gregkh@linuxfoundation.org, robh+dt@kernel.org, mark.rutland@arm.com, avifishman70@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, sumit.garg@linaro.org, jens.wiklander@linaro.org, vkoul@kernel.org, tglx@linutronix.de, joel@jms.id.au, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, openbmc@lists.ozlabs.org Subject: Re: [PATCH v1 1/2] dt-binding: hwrng: add NPCM RNG documentation Message-ID: <20190829104942.uyz5ms4m65hcqvmk@holly.lan> References: <20190828162617.237398-1-tmaimon77@gmail.com> <20190828162617.237398-2-tmaimon77@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190828162617.237398-2-tmaimon77@gmail.com> User-Agent: NeoMutt/20180716 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Wed, Aug 28, 2019 at 07:26:16PM +0300, Tomer Maimon wrote: > Added device tree binding documentation for Nuvoton BMC > NPCM Random Number Generator (RNG). > > Signed-off-by: Tomer Maimon > --- > .../bindings/rng/nuvoton,npcm-rng.txt | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rng/nuvoton,npcm-rng.txt > > diff --git a/Documentation/devicetree/bindings/rng/nuvoton,npcm-rng.txt b/Documentation/devicetree/bindings/rng/nuvoton,npcm-rng.txt > new file mode 100644 > index 000000000000..a697b4425fb3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/rng/nuvoton,npcm-rng.txt > @@ -0,0 +1,17 @@ > +NPCM SoC Random Number Generator > + > +Required properties: > +- compatible : "nuvoton,npcm750-rng" for the NPCM7XX BMC. > +- reg : Specifies physical base address and size of the registers. > + > +Optional property: > +- quality : estimated number of bits of true entropy per 1024 bits > + read from the rng. > + If this property is not defined, it defaults to 1000. Having a controllable quality implies that the numeric quality of the peripheral changes when it is stamped out on different SoCs (otherwise the driver can confidently set the quality without needing any hint from the DT). Is that really true here? Daniel. > + > +Example: > + > +rng: rng@f000b000 { > + compatible = "nuvoton,npcm750-rng"; > + reg = <0xf000b000 0x8>; > +}; > -- > 2.18.0 >