From: Eric Biggers <ebiggers@kernel.org>
To: linux-crypto@vger.kernel.org, linux-riscv@lists.infradead.org,
Jerry Shih <jerry.shih@sifive.com>
Cc: linux-kernel@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Phoebe Chen <phoebe.chen@sifive.com>,
hongrong.hsu@sifive.com, Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andy Chiu <andy.chiu@sifive.com>,
Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: [RFC PATCH 03/13] RISC-V: add helper function to read the vector VLEN
Date: Tue, 2 Jan 2024 00:47:29 -0600 [thread overview]
Message-ID: <20240102064743.220490-4-ebiggers@kernel.org> (raw)
In-Reply-To: <20240102064743.220490-1-ebiggers@kernel.org>
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
VLEN describes the length of each vector register and some instructions
need specific minimal VLENs to work correctly.
The vector code already includes a variable riscv_v_vsize that contains
the value of "32 vector registers with vlenb length" that gets filled
during boot. vlenb is the value contained in the CSR_VLENB register and
the value represents "VLEN / 8".
So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
users when they need to check the available VLEN.
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
---
arch/riscv/include/asm/vector.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 71af3404fda14..ae724e016fe24 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -218,11 +218,22 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
#define riscv_v_vsize (0)
#define riscv_v_vstate_discard(regs) do {} while (0)
#define riscv_v_vstate_save(task, regs) do {} while (0)
#define riscv_v_vstate_restore(task, regs) do {} while (0)
#define __switch_to_vector(__prev, __next) do {} while (0)
#define riscv_v_vstate_off(regs) do {} while (0)
#define riscv_v_vstate_on(regs) do {} while (0)
#endif /* CONFIG_RISCV_ISA_V */
+/*
+ * Return the implementation's vlen value.
+ *
+ * riscv_v_vsize contains the value of "32 vector registers with vlenb length"
+ * so rebuild the vlen value in bits from it.
+ */
+static inline int riscv_vector_vlen(void)
+{
+ return riscv_v_vsize / 32 * 8;
+}
+
#endif /* ! __ASM_RISCV_VECTOR_H */
--
2.43.0
next prev parent reply other threads:[~2024-01-02 6:50 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-02 6:47 [RFC PATCH 00/13] RISC-V crypto with reworked asm files Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 01/13] riscv: Add support for kernel mode vector Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 02/13] riscv: vector: make Vector always available for softirq context Eric Biggers
2024-01-02 6:47 ` Eric Biggers [this message]
2024-01-02 6:47 ` [RFC PATCH 04/13] RISC-V: add TOOLCHAIN_HAS_VECTOR_CRYPTO Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 05/13] RISC-V: hook new crypto subdir into build-system Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 06/13] crypto: riscv - add vector crypto accelerated AES Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 07/13] crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS} Eric Biggers
2024-01-03 14:50 ` Eric Biggers
2024-01-04 8:47 ` Jerry Shih
2024-01-04 17:18 ` Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 08/13] crypto: riscv - add vector crypto accelerated ChaCha20 Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 09/13] crypto: riscv - add vector crypto accelerated GHASH Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 10/13] crypto: riscv - add vector crypto accelerated SHA-{256,224} Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 11/13] crypto: riscv - add vector crypto accelerated SHA-{512,384} Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 12/13] crypto: riscv - add vector crypto accelerated SM3 Eric Biggers
2024-01-02 6:47 ` [RFC PATCH 13/13] crypto: riscv - add vector crypto accelerated SM4 Eric Biggers
2024-01-03 14:00 ` [RFC PATCH 00/13] RISC-V crypto with reworked asm files Ard Biesheuvel
2024-01-03 14:35 ` Eric Biggers
2024-01-04 10:23 ` Jerry Shih
2024-01-04 18:02 ` Eric Biggers
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