Re: [PATCH v8 13/16] crypto: caam - select DMA address size at runtime

From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: "Horia Geantă" <horia.geanta@nxp.com>
Cc: Chris Spencer <christopher.spencer@sea.co.uk>,
	Cory Tusar <cory.tusar@zii.aero>, Chris Healy <cphealy@gmail.com>,
	Lucas Stach <l.stach@pengutronix.de>,
	Aymen Sghaier <aymen.sghaier@nxp.com>,
	Leonard Crestez <leonard.crestez@nxp.com>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	linux-crypto@vger.kernel.org
Subject: Re: [PATCH v8 13/16] crypto: caam - select DMA address size at runtime
Date: Tue, 20 Aug 2019 13:29:07 -0700	[thread overview]
Message-ID: <CAHQ1cqFWEmJsE1XrUBVvGqp-aEy5HE6GO18DX+y0kOGsc7PbMw@mail.gmail.com> (raw)
In-Reply-To: <20190820202402.24951-14-andrew.smirnov@gmail.com>

On Tue, Aug 20, 2019 at 1:24 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
> i.MX8 mScale SoC still use 32-bit addresses in its CAAM implmentation,
> so we can't rely on sizeof(dma_addr_t) to detemine CAAM pointer
> size. Convert the code to query CTPR and MCFGR for that during driver
> probing.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Chris Spencer <christopher.spencer@sea.co.uk>
> Cc: Cory Tusar <cory.tusar@zii.aero>
> Cc: Chris Healy <cphealy@gmail.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Horia Geantă <horia.geanta@nxp.com>
> Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
> Cc: Leonard Crestez <leonard.crestez@nxp.com>
> Cc: linux-crypto@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  drivers/crypto/caam/caampkc.c     |  8 +++----
>  drivers/crypto/caam/ctrl.c        |  5 +++-
>  drivers/crypto/caam/desc_constr.h | 10 ++++++--
>  drivers/crypto/caam/intern.h      |  2 +-
>  drivers/crypto/caam/pdb.h         | 16 +++++++++----
>  drivers/crypto/caam/pkc_desc.c    |  8 +++----
>  drivers/crypto/caam/regs.h        | 40 +++++++++++++++++++++++--------
>  7 files changed, 63 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c
> index 5b12b232ee5e..83f96d4f86e0 100644
> --- a/drivers/crypto/caam/caampkc.c
> +++ b/drivers/crypto/caam/caampkc.c
> @@ -17,13 +17,13 @@
>  #include "sg_sw_sec4.h"
>  #include "caampkc.h"
>
> -#define DESC_RSA_PUB_LEN       (2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))
> +#define DESC_RSA_PUB_LEN       (2 * CAAM_CMD_SZ + SIZEOF_RSA_PUB_PDB)
>  #define DESC_RSA_PRIV_F1_LEN   (2 * CAAM_CMD_SZ + \
> -                                sizeof(struct rsa_priv_f1_pdb))
> +                                SIZEOF_RSA_PRIV_F1_PDB)
>  #define DESC_RSA_PRIV_F2_LEN   (2 * CAAM_CMD_SZ + \
> -                                sizeof(struct rsa_priv_f2_pdb))
> +                                SIZEOF_RSA_PRIV_F2_PDB)
>  #define DESC_RSA_PRIV_F3_LEN   (2 * CAAM_CMD_SZ + \
> -                                sizeof(struct rsa_priv_f3_pdb))
> +                                SIZEOF_RSA_PRIV_F3_PDB)
>  #define CAAM_RSA_MAX_INPUT_SIZE        512 /* for a 4096-bit modulus */
>
>  /* buffer filled with zeros, used for padding */
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
> index 47b92451756f..4b7f95f64e34 100644
> --- a/drivers/crypto/caam/ctrl.c
> +++ b/drivers/crypto/caam/ctrl.c
> @@ -602,7 +602,10 @@ static int caam_probe(struct platform_device *pdev)
>         caam_imx = (bool)imx_soc_match;
>
>         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
> -       caam_ptr_sz = sizeof(dma_addr_t);
> +       if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)

Horia:

As I previously mentioned, i.MX8MQ SRM I have doesn't document MCFGR
bits related to this. If you don't mind, please double check that
using MCFGR_LONG_PTR here is correct.

Thanks,
Andrey Smirnov