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x-originating-ip: [212.146.100.6] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6130c1b6-7258-43b9-d90a-08d7197e269f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:VI1PR0402MB3519; x-ms-traffictypediagnostic: VI1PR0402MB3519: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; x-forefront-prvs: 01208B1E18 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6029001)(4636009)(346002)(396003)(136003)(39860400002)(376002)(366004)(189003)(199004)(52536014)(14454004)(81166006)(256004)(4326008)(71200400001)(66556008)(76176011)(66476007)(53936002)(81156014)(229853002)(186003)(102836004)(8936002)(305945005)(7696005)(66946007)(7736002)(86362001)(71190400001)(55016002)(68736007)(64756008)(9686003)(44832011)(2501003)(446003)(74316002)(5660300002)(6246003)(91956017)(53546011)(33656002)(316002)(6116002)(99286004)(110136005)(54906003)(478600001)(8676002)(3846002)(486006)(2906002)(6436002)(25786009)(476003)(76116006)(6506007)(66446008)(66066001)(26005);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0402MB3519;H:VI1PR0402MB3485.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: hz9XACouxVHOKO0woj/vSVE/jihpZ+O1vFw8OVaAfd1XL7ZxYgsC+2TrPJRMb6zS7njXfQS8Np2fwZ+sw4Xn84tyYD83z3w/hhp5cXSLsk+zkecLo67Hi+jlEPNQvzRzKKf3aiiF6IkrEhf/GEffNnYJvQ6locDBVQfSQYRhJt0otMpzz6IcAIuajQkcBvnBeathXhvprKRXHkJ77G7EMUCWXF1DIcItXJM/S7TQMwaa9tVP1LsULKffPQqbp+ZhdludAdY0y/Hdc5o3nsMvAmNqOYRBxbsC8VMe6pqh0vnUfsEyW9siyDRUpnLn7W6oljmJFv3DxqMsUbiUowrXm2HtQuRiR4pAHrcABJgupzJAd+v3iRzEfpCYFbuXMAiTbXJJBTU2HmniKuUqZ/SgTXBJoHHC2kq5De6mP3Z4O+4= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6130c1b6-7258-43b9-d90a-08d7197e269f X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2019 08:23:10.0338 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: horia.geanta@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3519 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 7/17/2019 6:25 PM, Andrey Smirnov wrote:=0A= > i.MX8 SoC still use 32-bit addresses in its CAAM implmentation, so=0A= i.MX8 SoC or i.MX8 mScale?=0A= Looking at the documentation, some i.MX8 parts (for e.g. QM and QXP)=0A= allow for 36-bit addresses.=0A= =0A= > change all of the code to be able to handle that.=0A= > =0A= Shouldn't this case (32-bit CAAM and CONFIG_ARCH_DMA_ADDR_T_64BIT=3Dy) work= =0A= for any ARMv8 SoC, i.e. how is this i.MX-specific?=0A= =0A= > @@ -603,11 +603,13 @@ static int caam_probe(struct platform_device *pdev)= =0A= > ret =3D init_clocks(dev, ctrlpriv, imx_soc_match->data);=0A= > if (ret)=0A= > return ret;=0A= > +=0A= > + caam_ptr_sz =3D sizeof(u32);=0A= > + } else {=0A= > + caam_ptr_sz =3D sizeof(dma_addr_t);=0A= caam_ptr_sz should be deduced by reading MCFGR[PS] bit, i.e. decoupled=0A= from dma_addr_t.=0A= =0A= There is another configuration that should be considered=0A= (even though highly unlikely):=0A= caam_ptr_sz=3D1 - > 32-bit addresses for CAAM=0A= CONFIG_ARCH_DMA_ADDR_T_64BIT=3Dn - 32-bit dma_addr_t=0A= so the logic has to be carefully evaluated.=0A= =0A= > @@ -191,7 +191,8 @@ static inline u64 caam_dma64_to_cpu(u64 value)=0A= > =0A= > static inline u64 cpu_to_caam_dma(u64 value)=0A= > {=0A= > - if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))=0A= > + if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&=0A= > + !caam_imx)=0A= Related to my previous comment (i.MX-specific vs. SoC-generic),=0A= this should probably change to smth. like: caam_ptr_sz =3D=3D sizeof(u64)= =0A= =0A= > return cpu_to_caam_dma64(value);=0A= > else=0A= > return cpu_to_caam32(value);=0A= > @@ -199,7 +200,8 @@ static inline u64 cpu_to_caam_dma(u64 value)=0A= > =0A= > static inline u64 caam_dma_to_cpu(u64 value)=0A= > {=0A= > - if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))=0A= > + if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&=0A= > + !caam_imx)=0A= Same here.=0A= =0A= > return caam_dma64_to_cpu(value);=0A= > else=0A= > return caam32_to_cpu(value);=0A= > @@ -213,13 +215,24 @@ static inline u64 caam_dma_to_cpu(u64 value)=0A= > static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t= *desc,=0A= > u32 *jrstatus)=0A= > {=0A= > - struct {=0A= > - dma_addr_t desc;/* Pointer to completed descriptor */=0A= > - u32 jrstatus; /* Status for completed descriptor */=0A= > - } __packed *outentry =3D outring;=0A= > =0A= > - *desc =3D outentry[hw_idx].desc;=0A= > - *jrstatus =3D outentry[hw_idx].jrstatus;=0A= > + if (caam_imx) {=0A= Same here: if (caam_ptr_sz =3D=3D sizeof(u32))=0A= =0A= > + struct {=0A= > + u32 desc;=0A= > + u32 jrstatus;=0A= > + } __packed *outentry =3D outring;=0A= > +=0A= > + *desc =3D outentry[hw_idx].desc;=0A= > + *jrstatus =3D outentry[hw_idx].jrstatus;=0A= > + } else {=0A= > + struct {=0A= > + dma_addr_t desc;/* Pointer to completed descriptor */=0A= > + u32 jrstatus; /* Status for completed descriptor */=0A= > + } __packed *outentry =3D outring;=0A= > +=0A= > + *desc =3D outentry[hw_idx].desc;=0A= > + *jrstatus =3D outentry[hw_idx].jrstatus;=0A= > + }=0A= > }=0A= > =0A= > #define SIZEOF_JR_OUTENTRY (caam_ptr_sz + sizeof(u32))=0A= > @@ -246,9 +259,15 @@ static inline u32 jr_outentry_jrstatus(void *outring= , int hw_idx)=0A= > =0A= > static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t= val)=0A= > {=0A= > - dma_addr_t *inpentry =3D inpring;=0A= > + if (caam_imx) {=0A= And here: if (caam_ptr_sz =3D=3D sizeof(u32))=0A= =0A= > + u32 *inpentry =3D inpring;=0A= > =0A= > - inpentry[hw_idx] =3D val;=0A= > + inpentry[hw_idx] =3D val;=0A= > + } else {=0A= > + dma_addr_t *inpentry =3D inpring;=0A= > +=0A= > + inpentry[hw_idx] =3D val;=0A= > + }=0A= > }=0A= =0A= Horia=0A=