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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 3Ajs+YTKMgb0CLnQTjYSZpm2N1+6OObJgLTCUI3S27FWD/u/q8MXGXDAXdXbmWMom9JGwUkAUBAud36SPvqnmO01W6MQo4rgQnboiiFxZj8xjvD7i1mVgMCNy1WYUTqXfo7+0+NdebP0lF11qs+1AcYTzXQ7lzLFExqQ63c1Skxx08UQ1XdK9PhQBrb/RJXQNqsBWnqu2TG19V86EoM0yYa6f4cluixkAUjkW3u380fwkhq6YNJh/XztIfMvHig4jD0QMM6reiett/EfuGVD6FtR/IjhMyGVz1xq1rT2rP1gcThQNPS2Lxcviyte+5kdwptschyj/XhWp0j5A6lI0UjwgvsDouLXZ9xm08YMKcbbKfhjTJEjI16xoGjNhoDBNQxOCPGqW/YcHBGU//svMbH0w2NlEScswvXmQAT68vs= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e8bf53b-318f-429e-283e-08d71ff3781f X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Aug 2019 13:38:04.7906 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: r4WNdfPLdcfBI+nIhDClaByIDIkUldbf56YTTqqrKPTyDdAtPsegXXFUYHw+/uYzPffMtf2nRE+pFvai7PhhMg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3630 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 8/12/2019 10:27 PM, Andrey Smirnov wrote:=0A= > On Mon, Aug 5, 2019 at 1:23 AM Horia Geanta wrote:= =0A= >>=0A= >> On 7/17/2019 6:25 PM, Andrey Smirnov wrote:=0A= >>> @@ -603,11 +603,13 @@ static int caam_probe(struct platform_device *pde= v)=0A= >>> ret =3D init_clocks(dev, ctrlpriv, imx_soc_match->data);= =0A= >>> if (ret)=0A= >>> return ret;=0A= >>> +=0A= >>> + caam_ptr_sz =3D sizeof(u32);=0A= >>> + } else {=0A= >>> + caam_ptr_sz =3D sizeof(dma_addr_t);=0A= >> caam_ptr_sz should be deduced by reading MCFGR[PS] bit, i.e. decoupled= =0A= >> from dma_addr_t.=0A= >>=0A= > =0A= > MCFGR[PS] is not mentioned in i.MX8MQ SRM and MCFG_PS in CTPR_MS is=0A= > documented as set to "0" (seems to match in real HW as well). Doesn't=0A= > seem like a workable solution for i.MX8MQ. Is there something I am=0A= > missing?=0A= > =0A= If CTPR_MS[PS]=3D0, this means CAAM does not allow choosing the "pointer si= ze"=0A= via MCFGR[PS]. Usually in this case the RM does not document MCFGR[PS] bit,= =0A= which is identical to MCFGR[PS]=3D0.=0A= =0A= Thus the logic should be smth. like:=0A= caam_ptr_sz =3D CTPR_MS[PS] && MCFGR[PS] ? 64 : 32;=0A= =0A= >> There is another configuration that should be considered=0A= >> (even though highly unlikely):=0A= >> caam_ptr_sz=3D1 - > 32-bit addresses for CAAM=0A= >> CONFIG_ARCH_DMA_ADDR_T_64BIT=3Dn - 32-bit dma_addr_t=0A= >> so the logic has to be carefully evaluated.=0A= >>=0A= > =0A= > I don't understand what you mean here. 32-bit CAAM + 32-bit dma_addr_t=0A= > should already be the case for i.MX6, etc. how is what you describe=0A= > different?=0A= > =0A= Sorry for not being clear.=0A= =0A= caam_ptr_sz=3D1 - > 32-bit addresses for CAAM=0A= should have been=0A= caam_ptr_sz=3D*64* - > 32-bit addresses for CAAM=0A= i.e. CAAM address has "more than" (>) 32 bits (exact number of bits is=0A= SoC / chassis specific) and thus will be represented on 8 bytes.=0A= =0A= Thanks,=0A= Horia=0A=