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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 64sm3103622otm.37.2021.11.15.10.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 10:25:32 -0800 (PST) Date: Mon, 15 Nov 2021 12:25:27 -0600 From: Bjorn Andersson To: Bhupesh Sharma Cc: linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, agross@kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, stephan@gerhold.net, Thara Gopinath Subject: Re: [PATCH v5 14/22] crypto: qce: core: Add support to initialize interconnect path Message-ID: References: <20211110105922.217895-1-bhupesh.sharma@linaro.org> <20211110105922.217895-15-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211110105922.217895-15-bhupesh.sharma@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Wed 10 Nov 04:59 CST 2021, Bhupesh Sharma wrote: > From: Thara Gopinath > > Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 > etc. requires interconnect path between the engine and memory to be > explicitly enabled and bandwidth set prior to any operations. Add support > in the qce core to enable the interconnect path appropriately. > > Cc: Bjorn Andersson > Cc: Rob Herring > Signed-off-by: Bhupesh Sharma > [Make header file inclusion alphabetical and use devm_of_icc_get()] > Signed-off-by: Thara Gopinath > --- > drivers/crypto/qce/core.c | 34 +++++++++++++++++++++++++++------- > drivers/crypto/qce/core.h | 1 + > 2 files changed, 28 insertions(+), 7 deletions(-) > > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c > index d3780be44a76..89d9c01ba009 100644 > --- a/drivers/crypto/qce/core.c > +++ b/drivers/crypto/qce/core.c > @@ -5,6 +5,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -22,6 +23,8 @@ > #define QCE_MAJOR_VERSION5 0x05 > #define QCE_QUEUE_LENGTH 1 > > +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 > + > static const struct qce_algo_ops *qce_ops[] = { > #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER > &skcipher_ops, > @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev) > if (ret < 0) > return ret; > > + qce->mem_path = devm_of_icc_get(qce->dev, "memory"); > + if (IS_ERR(qce->mem_path)) > + return PTR_ERR(qce->mem_path); > + > qce->core = devm_clk_get(qce->dev, "core"); > - if (IS_ERR(qce->core)) > - return PTR_ERR(qce->core); > + if (IS_ERR(qce->core)) { > + ret = PTR_ERR(qce->core); > + goto err; I don't see a reason here, or in the following patches to move from return to goto here. Regards, Bjorn > + } > > qce->iface = devm_clk_get(qce->dev, "iface"); > - if (IS_ERR(qce->iface)) > - return PTR_ERR(qce->iface); > + if (IS_ERR(qce->iface)) { > + ret = PTR_ERR(qce->iface); > + goto err; > + } > > qce->bus = devm_clk_get(qce->dev, "bus"); > - if (IS_ERR(qce->bus)) > - return PTR_ERR(qce->bus); > + if (IS_ERR(qce->bus)) { > + ret = PTR_ERR(qce->bus); > + goto err; > + } > + > + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); > + if (ret) > + goto err; > > ret = clk_prepare_enable(qce->core); > if (ret) > - return ret; > + goto err_mem_path_disable; > > ret = clk_prepare_enable(qce->iface); > if (ret) > @@ -260,6 +277,9 @@ static int qce_crypto_probe(struct platform_device *pdev) > clk_disable_unprepare(qce->iface); > err_clks_core: > clk_disable_unprepare(qce->core); > +err_mem_path_disable: > + icc_set_bw(qce->mem_path, 0, 0); > +err: > return ret; > } > > diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h > index 085774cdf641..228fcd69ec51 100644 > --- a/drivers/crypto/qce/core.h > +++ b/drivers/crypto/qce/core.h > @@ -35,6 +35,7 @@ struct qce_device { > void __iomem *base; > struct device *dev; > struct clk *core, *iface, *bus; > + struct icc_path *mem_path; > struct qce_dma_data dma; > int burst_size; > unsigned int pipe_pair_id; > -- > 2.31.1 >