From: "Andy Lutomirski" <luto@kernel.org>
To: "Dey, Megha" <megha.dey@intel.com>,
"Dave Hansen" <dave.hansen@intel.com>,
"Herbert Xu" <herbert@gondor.apana.org.au>
Cc: "Tony Luck" <tony.luck@intel.com>,
"Asit K Mallick" <asit.k.mallick@intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
"Linux Crypto Mailing List" <linux-crypto@vger.kernel.org>,
"David S. Miller" <davem@davemloft.net>,
"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
"Chen, Tim C" <tim.c.chen@intel.com>,
"Kleen, Andi" <andi.kleen@intel.com>,
greg.b.tucker@intel.com, rajendrakumar.chinnaiyan@intel.com,
tomasz.kantecki@intel.com, ryan.d.saffores@intel.com,
"Ira Weiny" <ira.weiny@intel.com>,
"Eric Biggers" <ebiggers@kernel.org>,
"Ard Biesheuvel" <ardb@kernel.org>,
"the arch/x86 maintainers" <x86@kernel.org>,
anirudh.venkataramanan@intel.com
Subject: Re: [RFC V2 0/5] Introduce AVX512 optimized crypto algorithms
Date: Sat, 05 Mar 2022 10:37:56 -0800 [thread overview]
Message-ID: <ba4b74eb-29b9-43b0-9e94-09b696f18961@www.fastmail.com> (raw)
In-Reply-To: <0a21fe4d-b135-3696-71f0-aa14ca715d51@intel.com>
On Thu, Feb 24, 2022, at 11:31 AM, Dey, Megha wrote:
> Hi all,
>
> On 1/31/2022 11:18 AM, Dave Hansen wrote:
>> On 1/31/22 10:43, Dey, Megha wrote:
>>> With this implementation, we see a 1.5X improvement on ICX/ICL for 16KB
>>> buffers compared to the existing kernel AES-GCM implementation that
>>> works on 128-bit XMM registers.
>> What is your best guess about how future-proof this implementation is?
>>
>> Will this be an ICL/ICX one-off? Or, will implementations using 256-bit
>> YMM registers continue to enjoy a frequency advantage over the 512-bit
>> implementations for a long time?
>
> Dave,
>
> This would not be an ICL/ICX one off. For the foreseeable future,
> AVX512VL YMM implementations will enjoy a frequency advantage over
> AVX512L ZMM implementations.
>
> Although, over time, ZMM and YMM will converge when it comes to performance.
>
> Herbert/Andy,
>
> Could you please let us know if this approach is a viable one and would
> be acceptable by the community?
>
> Optimizing crypto algorithms using AVX512VL instructions gives a 1.5X
> performance improvement over existing AES-GCM algorithm in the
> kernel(using XMM registers) with no frequency drop.
I'm assuming this would be enabled automatically without needing any special command line options. If so, it seems reasonable to me.
--Andy
next prev parent reply other threads:[~2022-03-05 18:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-23 7:28 [RFC V2 0/5] Introduce AVX512 optimized crypto algorithms Megha Dey
2021-01-23 7:28 ` [RFC V2 1/5] crypto: aesni - fix coding style for if/else block Megha Dey
2021-01-23 7:28 ` [RFC V2 2/5] x86: Probe assembler capabilities for VAES and VPLCMULQDQ support Megha Dey
2021-01-23 7:28 ` [RFC V2 3/5] crypto: crct10dif - Accelerated CRC T10 DIF with vectorized instruction Megha Dey
2021-01-23 7:28 ` [RFC V2 4/5] crypto: aesni - AES CTR x86_64 "by16" AVX512 optimization Megha Dey
2021-01-23 7:28 ` [RFC V2 5/5] crypto: aesni - AVX512 version of AESNI-GCM using VPCLMULQDQ Megha Dey
2021-01-24 16:23 ` [RFC V2 0/5] Introduce AVX512 optimized crypto algorithms Andy Lutomirski
2021-02-24 0:54 ` Dey, Megha
2021-02-24 17:42 ` Andy Lutomirski
2022-01-31 18:43 ` Dey, Megha
2022-01-31 19:18 ` Dave Hansen
2022-02-01 16:42 ` Dey, Megha
2022-02-24 19:31 ` Dey, Megha
2022-03-05 18:37 ` Andy Lutomirski [this message]
2021-05-07 16:22 ` Dave Hansen
2021-01-25 17:27 ` Dave Hansen
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