From: Waiman Long <longman@redhat.com>
To: Stafford Horne <shorne@gmail.com>, Boqun Feng <boqun.feng@gmail.com>
Cc: guoren@kernel.org, linux-arch@vger.kernel.org,
linux-xtensa@linux-xtensa.org, Guo Ren <guoren@linux.alibaba.com>,
Arnd Bergmann <arnd@arndb.de>,
Peter Zijlstra <peterz@infradead.org>,
Will Deacon <will@kernel.org>,
linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org,
openrisc@lists.librecores.org, Anup Patel <anup@brainfault.org>,
sparclinux@vger.kernel.org, linux-riscv@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org, Ingo Molnar <mingo@redhat.com>
Subject: Re: [OpenRISC] [PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Thu, 8 Apr 2021 15:00:59 -0400 [thread overview]
Message-ID: <1199af5f-275a-5812-fc73-f1d33449036b@redhat.com> (raw)
In-Reply-To: <20210406235208.GG3288043@lianli.shorne-pla.net>
On 4/6/21 7:52 PM, Stafford Horne wrote:
>
> For OpenRISC I did ack the patch to convert to
> CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32=y. But I think you are right, the
> generic code in xchg_tail and the xchg16 emulation code in produced by OpenRISC
> using xchg32 would produce very similar code. I have not compared instructions,
> but it does seem like duplicate functionality.
>
> Why doesn't RISC-V add the xchg16 emulation code similar to OpenRISC? For
> OpenRISC we added xchg16 and xchg8 emulation code to enable qspinlocks. So
> one thought is with CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32=y, can we remove our
> xchg16/xchg8 emulation code?
For the record, the latest qspinlock code doesn't use xchg8 anymore. It
still need xchg16, though.
Cheers,
Longman
next prev parent reply other threads:[~2021-04-08 19:01 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 14:30 [PATCH v6 0/9] riscv: Add qspinlock/qrwlock guoren
2021-03-31 14:30 ` [PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-04-06 16:51 ` Boqun Feng
2021-04-06 23:52 ` [OpenRISC] " Stafford Horne
2021-04-07 9:47 ` Peter Zijlstra
2021-04-07 20:12 ` Stafford Horne
2021-04-08 19:00 ` Waiman Long [this message]
2021-03-31 14:30 ` [PATCH v6 2/9] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-31 14:30 ` [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation guoren
2021-04-05 5:54 ` Guo Ren
2021-04-11 16:02 ` Guo Ren
2021-04-11 16:51 ` Guo Ren
2021-03-31 14:30 ` [PATCH v6 4/9] csky: locks: Optimize coding convention guoren
2021-04-11 16:01 ` Guo Ren
2021-03-31 14:30 ` [PATCH v6 5/9] csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-31 14:30 ` [PATCH v6 6/9] openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-04-06 8:56 ` Stafford Horne
2021-03-31 14:30 ` [PATCH v6 7/9] sparc: " guoren
2021-03-31 14:30 ` [PATCH v6 8/9] xtensa: " guoren
2021-03-31 14:30 ` [PATCH v6 9/9] powerpc/qspinlock: " guoren
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