* [PATCH v3 1/4] riscv: cmpxchg.h: Cleanup unused code
2021-03-25 7:55 [PATCH v3 0/4] riscv: Add qspinlock/qrwlock guoren
@ 2021-03-25 7:55 ` guoren
2021-03-25 7:55 ` [PATCH v3 2/4] riscv: cmpxchg.h: Merge macros guoren
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: guoren @ 2021-03-25 7:55 UTC (permalink / raw)
To: guoren, Anup.Patel
Cc: linux-riscv, linux-kernel, linux-csky, linux-arch,
tech-unixplatformspec, Guo Ren, Peter Zijlstra, Michael Clark,
Anup Patel, Arnd Bergmann, Palmer Dabbelt
From: Guo Ren <guoren@linux.alibaba.com>
Remove unnecessary marco, they are no use or handled by generic
files (atomic-fallback.h, asm-generic/cmpxchg*).
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Link: https://lore.kernel.org/linux-riscv/CAJF2gTT1_mP-wiK2HsCpTeU61NqZVKZX1A5ye=TwqvGN4TPmrA@mail.gmail.com/
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Michael Clark <michaeljclark@mac.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/include/asm/cmpxchg.h | 83 --------------------------------
1 file changed, 83 deletions(-)
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 262e5bbb2776..f1383c15e16b 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -72,13 +72,6 @@
__ret; \
})
-#define xchg_acquire(ptr, x) \
-({ \
- __typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg_acquire((ptr), \
- _x_, sizeof(*(ptr))); \
-})
-
#define __xchg_release(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -107,13 +100,6 @@
__ret; \
})
-#define xchg_release(ptr, x) \
-({ \
- __typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg_release((ptr), \
- _x_, sizeof(*(ptr))); \
-})
-
#define __xchg(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -140,24 +126,6 @@
__ret; \
})
-#define xchg(ptr, x) \
-({ \
- __typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg((ptr), _x_, sizeof(*(ptr))); \
-})
-
-#define xchg32(ptr, x) \
-({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
- xchg((ptr), (x)); \
-})
-
-#define xchg64(ptr, x) \
-({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
- xchg((ptr), (x)); \
-})
-
/*
* Atomic compare and exchange. Compare OLD with MEM, if identical,
* store NEW in MEM. Return the initial value in MEM. Success is
@@ -245,14 +213,6 @@
__ret; \
})
-#define cmpxchg_acquire(ptr, o, n) \
-({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg_acquire((ptr), \
- _o_, _n_, sizeof(*(ptr))); \
-})
-
#define __cmpxchg_release(ptr, old, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -291,14 +251,6 @@
__ret; \
})
-#define cmpxchg_release(ptr, o, n) \
-({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg_release((ptr), \
- _o_, _n_, sizeof(*(ptr))); \
-})
-
#define __cmpxchg(ptr, old, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -337,39 +289,4 @@
__ret; \
})
-#define cmpxchg(ptr, o, n) \
-({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg((ptr), \
- _o_, _n_, sizeof(*(ptr))); \
-})
-
-#define cmpxchg_local(ptr, o, n) \
- (__cmpxchg_relaxed((ptr), (o), (n), sizeof(*(ptr))))
-
-#define cmpxchg32(ptr, o, n) \
-({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
- cmpxchg((ptr), (o), (n)); \
-})
-
-#define cmpxchg32_local(ptr, o, n) \
-({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
- cmpxchg_relaxed((ptr), (o), (n)) \
-})
-
-#define cmpxchg64(ptr, o, n) \
-({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
- cmpxchg((ptr), (o), (n)); \
-})
-
-#define cmpxchg64_local(ptr, o, n) \
-({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
- cmpxchg_relaxed((ptr), (o), (n)); \
-})
-
#endif /* _ASM_RISCV_CMPXCHG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 2/4] riscv: cmpxchg.h: Merge macros
2021-03-25 7:55 [PATCH v3 0/4] riscv: Add qspinlock/qrwlock guoren
2021-03-25 7:55 ` [PATCH v3 1/4] riscv: cmpxchg.h: Cleanup unused code guoren
@ 2021-03-25 7:55 ` guoren
2021-03-25 7:55 ` [PATCH v3 3/4] riscv: cmpxchg.h: Implement xchg for short guoren
2021-03-25 7:55 ` [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
3 siblings, 0 replies; 8+ messages in thread
From: guoren @ 2021-03-25 7:55 UTC (permalink / raw)
To: guoren, Anup.Patel
Cc: linux-riscv, linux-kernel, linux-csky, linux-arch,
tech-unixplatformspec, Guo Ren, Peter Zijlstra, Michael Clark,
Anup Patel, Arnd Bergmann, Palmer Dabbelt
From: Guo Ren <guoren@linux.alibaba.com>
To reduce assembly codes, let's merge duplicate codes into one
(xchg_acquire, xchg_release, cmpxchg_release).
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Link: https://lore.kernel.org/linux-riscv/CAJF2gTT1_mP-wiK2HsCpTeU61NqZVKZX1A5ye=TwqvGN4TPmrA@mail.gmail.com/
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Michael Clark <michaeljclark@mac.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/include/asm/cmpxchg.h | 92 +++++---------------------------
1 file changed, 12 insertions(+), 80 deletions(-)
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index f1383c15e16b..50513b95411d 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -11,6 +11,12 @@
#include <asm/barrier.h>
#include <asm/fence.h>
+#define __local_acquire_fence() \
+ __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory")
+
+#define __local_release_fence() \
+ __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory")
+
#define __xchg_relaxed(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -46,58 +52,16 @@
#define __xchg_acquire(ptr, new, size) \
({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- " amoswap.w %0, %2, %1\n" \
- RISCV_ACQUIRE_BARRIER \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- " amoswap.d %0, %2, %1\n" \
- RISCV_ACQUIRE_BARRIER \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
+ __ret = __xchg_relaxed(ptr, new, size); \
+ __local_acquire_fence(); \
__ret; \
})
#define __xchg_release(ptr, new, size) \
({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(new) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- " amoswap.w %0, %2, %1\n" \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- " amoswap.d %0, %2, %1\n" \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
+ __local_release_fence(); \
+ __xchg_relaxed(ptr, new, size); \
})
#define __xchg(ptr, new, size) \
@@ -215,40 +179,8 @@
#define __cmpxchg_release(ptr, old, new, size) \
({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(*(ptr)) __old = (old); \
- __typeof__(*(ptr)) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- register unsigned int __rc; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- "0: lr.w %0, %2\n" \
- " bne %0, %z3, 1f\n" \
- " sc.w %1, %z4, %2\n" \
- " bnez %1, 0b\n" \
- "1:\n" \
- : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
- : "rJ" ((long)__old), "rJ" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- "0: lr.d %0, %2\n" \
- " bne %0, %z3, 1f\n" \
- " sc.d %1, %z4, %2\n" \
- " bnez %1, 0b\n" \
- "1:\n" \
- : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
- : "rJ" (__old), "rJ" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
+ __local_release_fence(); \
+ __cmpxchg_relaxed(ptr, old, new, size); \
})
#define __cmpxchg(ptr, old, new, size) \
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 3/4] riscv: cmpxchg.h: Implement xchg for short
2021-03-25 7:55 [PATCH v3 0/4] riscv: Add qspinlock/qrwlock guoren
2021-03-25 7:55 ` [PATCH v3 1/4] riscv: cmpxchg.h: Cleanup unused code guoren
2021-03-25 7:55 ` [PATCH v3 2/4] riscv: cmpxchg.h: Merge macros guoren
@ 2021-03-25 7:55 ` guoren
2021-03-25 7:55 ` [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
3 siblings, 0 replies; 8+ messages in thread
From: guoren @ 2021-03-25 7:55 UTC (permalink / raw)
To: guoren, Anup.Patel
Cc: linux-riscv, linux-kernel, linux-csky, linux-arch,
tech-unixplatformspec, Guo Ren, Peter Zijlstra, Anup Patel,
Arnd Bergmann, Palmer Dabbelt
From: Guo Ren <guoren@linux.alibaba.com>
riscv only support lr.wd/s(c).w(d) with word(double word) size &
align access. There are not lr.h/sc.h instructions. But qspinlock.c
need xchg with short type variable:
xchg_tail -> xchg_releaxed(&lock->tail, ...
typedef struct qspinlock {
union {
atomic_t val;
/*
* By using the whole 2nd least significant byte for the
* pending bit, we can allow better optimization of the lock
* acquisition for the pending bit holder.
*/
struct {
u8 locked;
u8 pending;
};
struct {
u16 locked_pending;
u16 tail; /* half word*/
};
};
} arch_spinlock_t;
So we add short emulation in xchg with word length and it only
solve qspinlock's requirement.
Michael has sent another implementation, see the Link below.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Michael Clark <michaeljclark@mac.com>
Tested-by: Guo Ren <guoren@linux.alibaba.com>
Link: https://lore.kernel.org/linux-riscv/20190211043829.30096-2-michaeljclark@mac.com/
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Anup Patel <anup@brainfault.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/include/asm/cmpxchg.h | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 50513b95411d..5ca41152cf4b 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -22,7 +22,43 @@
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
+ register unsigned long __rc, tmp, align, addr; \
switch (size) { \
+ case 2: \
+ align = ((unsigned long) __ptr & 0x3); \
+ addr = ((unsigned long) __ptr & ~0x3); \
+ if (align) { \
+ __asm__ __volatile__ ( \
+ "0: lr.w %0, (%4) \n" \
+ " mv %1, %0 \n" \
+ " slliw %1, %1, 16 \n" \
+ " srliw %1, %1, 16 \n" \
+ " mv %2, %3 \n" \
+ " slliw %2, %2, 16 \n" \
+ " or %1, %2, %1 \n" \
+ " sc.w %2, %1, (%4) \n" \
+ " bnez %2, 0b \n" \
+ " srliw %0, %0, 16 \n" \
+ : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
+ : "r" (__new), "r"(addr) \
+ : "memory"); \
+ } else { \
+ __asm__ __volatile__ ( \
+ "0: lr.w %0, (%4) \n" \
+ " mv %1, %0 \n" \
+ " srliw %1, %1, 16 \n" \
+ " slliw %1, %1, 16 \n" \
+ " mv %2, %3 \n" \
+ " or %1, %2, %1 \n" \
+ " sc.w %2, %1, 0(%4) \n" \
+ " bnez %2, 0b \n" \
+ " slliw %0, %0, 16 \n" \
+ " srliw %0, %0, 16 \n" \
+ : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
+ : "r" (__new), "r"(addr) \
+ : "memory"); \
+ } \
+ break; \
case 4: \
__asm__ __volatile__ ( \
" amoswap.w %0, %2, %1\n" \
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
2021-03-25 7:55 [PATCH v3 0/4] riscv: Add qspinlock/qrwlock guoren
` (2 preceding siblings ...)
2021-03-25 7:55 ` [PATCH v3 3/4] riscv: cmpxchg.h: Implement xchg for short guoren
@ 2021-03-25 7:55 ` guoren
2021-03-25 11:15 ` kernel test robot
3 siblings, 1 reply; 8+ messages in thread
From: guoren @ 2021-03-25 7:55 UTC (permalink / raw)
To: guoren, Anup.Patel
Cc: linux-riscv, linux-kernel, linux-csky, linux-arch,
tech-unixplatformspec, Michael Clark, Peter Zijlstra, Anup Patel,
Arnd Bergmann, Palmer Dabbelt
From: Michael Clark <michaeljclark@mac.com>
Update the RISC-V port to use the generic qspinlock and qrwlock.
This patch requires support for xchg for short which are added by
a previous patch.
Guo fixed up compile error which made by below include sequence:
+#include <asm/qrwlock.h>
+#include <asm/qspinlock.h>
Signed-off-by: Michael Clark <michaeljclark@mac.com>
Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
Tested-by: Guo Ren <guoren@linux.alibaba.com>
Link: https://lore.kernel.org/linux-riscv/20190211043829.30096-3-michaeljclark@mac.com/
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Anup Patel <anup@brainfault.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/Kconfig | 2 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
4 files changed, 10 insertions(+), 136 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 87d7b52f278f..c78b8b0ccf96 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -33,6 +33,8 @@ config RISCV
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
+ select ARCH_USE_QUEUED_RWLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 445ccc97305a..750c1056b90f 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -3,5 +3,8 @@ generic-y += early_ioremap.h
generic-y += extable.h
generic-y += flat.h
generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
+generic-y += qrwlock.h
+generic-y += qspinlock.h
generic-y += user.h
generic-y += vmlinux.lds.h
diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
index f4f7fa1b7ca8..a557de67a425 100644
--- a/arch/riscv/include/asm/spinlock.h
+++ b/arch/riscv/include/asm/spinlock.h
@@ -7,129 +7,7 @@
#ifndef _ASM_RISCV_SPINLOCK_H
#define _ASM_RISCV_SPINLOCK_H
-#include <linux/kernel.h>
-#include <asm/current.h>
-#include <asm/fence.h>
-
-/*
- * Simple spin lock operations. These provide no fairness guarantees.
- */
-
-/* FIXME: Replace this with a ticket lock, like MIPS. */
-
-#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int tmp = 1, busy;
-
- __asm__ __volatile__ (
- " amoswap.w %0, %2, %1\n"
- RISCV_ACQUIRE_BARRIER
- : "=r" (busy), "+A" (lock->lock)
- : "r" (tmp)
- : "memory");
-
- return !busy;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- while (1) {
- if (arch_spin_is_locked(lock))
- continue;
-
- if (arch_spin_trylock(lock))
- break;
- }
-}
-
-/***********************************************************/
-
-static inline void arch_read_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1b\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline void arch_write_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1b\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1f\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1f\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *lock)
-{
- __asm__ __volatile__(
- RISCV_RELEASE_BARRIER
- " amoadd.w x0, %1, %0\n"
- : "+A" (lock->lock)
- : "r" (-1)
- : "memory");
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
+#include <asm/qspinlock.h>
+#include <asm/qrwlock.h>
#endif /* _ASM_RISCV_SPINLOCK_H */
diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h
index f398e7638dd6..d033a973f287 100644
--- a/arch/riscv/include/asm/spinlock_types.h
+++ b/arch/riscv/include/asm/spinlock_types.h
@@ -6,20 +6,11 @@
#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
#define _ASM_RISCV_SPINLOCK_TYPES_H
-#ifndef __LINUX_SPINLOCK_TYPES_H
+#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(_ASM_RISCV_SPINLOCK_H)
# error "please don't include this file directly"
#endif
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { 0 }
+#include <asm-generic/qspinlock_types.h>
+#include <asm-generic/qrwlock_types.h>
#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
2021-03-25 7:55 ` [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
@ 2021-03-25 11:15 ` kernel test robot
2021-03-25 11:34 ` Guo Ren
0 siblings, 1 reply; 8+ messages in thread
From: kernel test robot @ 2021-03-25 11:15 UTC (permalink / raw)
To: guoren, Anup.Patel
Cc: kbuild-all, linux-riscv, linux-kernel, linux-csky, linux-arch,
tech-unixplatformspec, Michael Clark, Peter Zijlstra, Anup Patel
[-- Attachment #1: Type: text/plain, Size: 3193 bytes --]
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/locking/core]
[also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08
config: riscv-rv32_defconfig (attached as .config)
compiler: riscv32-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
kernel/locking/qspinlock.c: Assembler messages:
kernel/locking/qspinlock.c:184: Error: unrecognized opcode `srliw t1,t1,16'
kernel/locking/qspinlock.c:185: Error: unrecognized opcode `slliw t1,t1,16'
>> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16'
>> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16'
kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16'
kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'
>> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
vim +190 kernel/locking/qspinlock.c
69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
59fb586b4a07b4 Will Deacon 2018-04-26 193 */
59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
59fb586b4a07b4 Will Deacon 2018-04-26 195 {
59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
59fb586b4a07b4 Will Deacon 2018-04-26 197 }
59fb586b4a07b4 Will Deacon 2018-04-26 198
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 20563 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
2021-03-25 11:15 ` kernel test robot
@ 2021-03-25 11:34 ` Guo Ren
2021-03-25 11:52 ` Guo Ren
0 siblings, 1 reply; 8+ messages in thread
From: Guo Ren @ 2021-03-25 11:34 UTC (permalink / raw)
To: kernel test robot
Cc: Anup Patel, kbuild-all, linux-riscv, Linux Kernel Mailing List,
linux-csky, linux-arch, tech-unixplatformspec, Michael Clark,
Peter Zijlstra, Anup Patel
haha, I forgot RV32, it needs a
#ifdef RV32
srliw
#else
srli
#endif
On Thu, Mar 25, 2021 at 7:16 PM kernel test robot <lkp@intel.com> wrote:
>
> Hi,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on tip/locking/core]
> [also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08
> config: riscv-rv32_defconfig (attached as .config)
> compiler: riscv32-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
> git remote add linux-review https://github.com/0day-ci/linux
> git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> kernel/locking/qspinlock.c: Assembler messages:
> kernel/locking/qspinlock.c:184: Error: unrecognized opcode `srliw t1,t1,16'
> kernel/locking/qspinlock.c:185: Error: unrecognized opcode `slliw t1,t1,16'
> >> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16'
> >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16'
> kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16'
> kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'
> >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
>
>
> vim +190 kernel/locking/qspinlock.c
>
> 69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
> 59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
> 59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
> 59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
> 59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
> 59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
> 59fb586b4a07b4 Will Deacon 2018-04-26 193 */
> 59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
> 59fb586b4a07b4 Will Deacon 2018-04-26 195 {
> 59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
> 59fb586b4a07b4 Will Deacon 2018-04-26 197 }
> 59fb586b4a07b4 Will Deacon 2018-04-26 198
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
2021-03-25 11:34 ` Guo Ren
@ 2021-03-25 11:52 ` Guo Ren
0 siblings, 0 replies; 8+ messages in thread
From: Guo Ren @ 2021-03-25 11:52 UTC (permalink / raw)
To: kernel test robot
Cc: Anup Patel, kbuild-all, linux-riscv, Linux Kernel Mailing List,
linux-csky, linux-arch, tech-unixplatformspec, Michael Clark,
Peter Zijlstra, Anup Patel
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 5ca41152cf4b..894e170c503e 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -17,6 +17,14 @@
#define __local_release_fence()
\
__asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory")
+#ifdef CONFIG_32BIT
+#define __ASM_SLLIW "slli\t"
+#define __ASM_SRLIW "srli\t"
+#else
+#define __ASM_SLLIW "slliw\t"
+#define __ASM_SRLIW "srliw\t"
+#endif
+
#define __xchg_relaxed(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -31,14 +39,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " slliw %1, %1, 16 \n" \
- " srliw %1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
- " slliw %2, %2, 16 \n" \
+ __ASM_SLLIW "%2, %2, 16 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, (%4) \n" \
" bnez %2, 0b \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \
@@ -46,14 +54,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " srliw %1, %1, 16 \n" \
- " slliw %1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, 0(%4) \n" \
" bnez %2, 0b \n" \
- " slliw %0, %0, 16 \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SLLIW "%0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \
On Thu, Mar 25, 2021 at 7:34 PM Guo Ren <guoren@kernel.org> wrote:
>
> haha, I forgot RV32, it needs a
>
> #ifdef RV32
> srliw
> #else
> srli
> #endif
>
> On Thu, Mar 25, 2021 at 7:16 PM kernel test robot <lkp@intel.com> wrote:
> >
> > Hi,
> >
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on tip/locking/core]
> > [also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch]
> >
> > url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08
> > config: riscv-rv32_defconfig (attached as .config)
> > compiler: riscv32-linux-gcc (GCC) 9.3.0
> > reproduce (this is a W=1 build):
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
> > git remote add linux-review https://github.com/0day-ci/linux
> > git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> > git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
> > # save the attached .config to linux build tree
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <lkp@intel.com>
> >
> > All errors (new ones prefixed by >>):
> >
> > kernel/locking/qspinlock.c: Assembler messages:
> > kernel/locking/qspinlock.c:184: Error: unrecognized opcode `srliw t1,t1,16'
> > kernel/locking/qspinlock.c:185: Error: unrecognized opcode `slliw t1,t1,16'
> > >> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16'
> > >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> > kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16'
> > kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16'
> > kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'
> > >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> >
> >
> > vim +190 kernel/locking/qspinlock.c
> >
> > 69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
> > 59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
> > 59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
> > 59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
> > 59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
> > 59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
> > 59fb586b4a07b4 Will Deacon 2018-04-26 193 */
> > 59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
> > 59fb586b4a07b4 Will Deacon 2018-04-26 195 {
> > 59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
> > 59fb586b4a07b4 Will Deacon 2018-04-26 197 }
> > 59fb586b4a07b4 Will Deacon 2018-04-26 198
> >
> > ---
> > 0-DAY CI Kernel Test Service, Intel Corporation
> > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
>
>
>
> --
> Best Regards
> Guo Ren
>
> ML: https://lore.kernel.org/linux-csky/
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply related [flat|nested] 8+ messages in thread