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From: guoren@kernel.org
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, Anup.Patel@wdc.com,
	vincent.chen@sifive.com, zong.li@sifive.com,
	greentime.hu@sifive.com, bmeng.cn@gmail.com, atish.patra@wdc.com,
	schwab@linux-m68k.org
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	arnd@arndb.de, linux-csky@vger.kernel.org,
	linux-riscv@lists.infradead.org, Guo Ren <ren_guo@c-sky.com>
Subject: [PATCH V2 3/4] riscv: Extending cpufeature.c to detect V-extension
Date: Thu, 16 Jan 2020 22:30:28 +0800
Message-ID: <20200116143029.31441-3-guoren@kernel.org> (raw)
In-Reply-To: <20200116143029.31441-1-guoren@kernel.org>

From: Guo Ren <ren_guo@c-sky.com>

Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Anup Patel <Anup.Patel@wdc.com>
---
 arch/riscv/include/uapi/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c      | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index dee98ee28318..a913e9a38819 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
 #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
 #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
 #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
 
 #endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a5ad00043104..c8527d770c98 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -30,6 +30,7 @@ void riscv_fill_hwcap(void)
 	isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
 	isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+	isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
 
 	elf_hwcap = 0;
 
@@ -44,7 +45,8 @@ void riscv_fill_hwcap(void)
 			continue;
 		}
 
-		for (i = 0; i < strlen(isa); ++i)
+		/* Skip rv64/rv32 to support v/V:vector */
+		for (i = 4; i < strlen(isa); ++i)
 			this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
 
 		/*
-- 
2.17.0


  parent reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-16 14:30 [PATCH V2 1/4] riscv: Separate patch for cflags and aflags guoren
2020-01-16 14:30 ` [PATCH V2 2/4] riscv: Rename __switch_to_aux -> fpu guoren
2020-01-23  5:44   ` Anup Patel
2020-01-16 14:30 ` guoren [this message]
2020-01-23  5:45   ` [PATCH V2 3/4] riscv: Extending cpufeature.c to detect V-extension Anup Patel
2020-01-16 14:30 ` [PATCH V2 4/4] riscv: Add vector ISA support guoren
2020-01-23  6:04   ` Anup Patel
2020-01-23  5:44 ` [PATCH V2 1/4] riscv: Separate patch for cflags and aflags Anup Patel

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