From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 721E8C10F27 for ; Sun, 8 Mar 2020 09:53:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4AFFB2087F for ; Sun, 8 Mar 2020 09:53:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583661228; bh=UyEAFCtYH62bmOtlaU0++uKPtjONoRxQfLj5UKjAlfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=RHh2JaJLNWcoxHowQGHk/fqRYItdfKbhPWradS/EGc/XdWKUzAaqx4BIu7YhFkgrk UBXbqQYE3HaLwWQaQOZkzMB+R7yVNrsW2ZYbaTafuWtXqdIbQuLyxR2CWidOljbDEi Rx3y52OBrnEPN8BiKVNglbiggdw1sn3LHZJ3gPBw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726609AbgCHJxr (ORCPT ); Sun, 8 Mar 2020 05:53:47 -0400 Received: from mail.kernel.org ([198.145.29.99]:38076 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726645AbgCHJxq (ORCPT ); Sun, 8 Mar 2020 05:53:46 -0400 Received: from localhost.localdomain (unknown [89.208.247.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 183872146E; Sun, 8 Mar 2020 09:53:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583661226; bh=UyEAFCtYH62bmOtlaU0++uKPtjONoRxQfLj5UKjAlfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DrRo8Neg/25VQm0tAuBXtvFbqrCIXP+36X19GY2woYBNlWtd8SKh+RWY58zwaVsmr lKo3ooXStjQXfIhMbyg40fsP1pKG8OTWFEArcNsyKCIQ94oxp08JE3kr/bwpMKb6o9 YQhMcOE3DJO4w/EqxKDciBgdlhV0aq94DFUBMcyc= From: guoren@kernel.org To: paul.walmsley@sifive.com, palmer@dabbelt.com, Anup.Patel@wdc.com, greentime.hu@sifive.com Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, arnd@arndb.de, linux-csky@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Dave Martin Subject: [RFC PATCH V3 10/11] riscv: Add ptrace support Date: Sun, 8 Mar 2020 17:49:53 +0800 Message-Id: <20200308094954.13258-11-guoren@kernel.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20200308094954.13258-1-guoren@kernel.org> References: <20200308094954.13258-1-guoren@kernel.org> Sender: linux-csky-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-csky@vger.kernel.org From: Guo Ren Add new regset for vector and the implementation is similar to fpu. Signed-off-by: Guo Ren --- arch/riscv/include/uapi/asm/elf.h | 1 + arch/riscv/kernel/ptrace.c | 41 +++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 43 insertions(+) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..099434d075a7 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -23,6 +23,7 @@ typedef struct user_regs_struct elf_gregset_t; typedef __u64 elf_fpreg_t; typedef union __riscv_fp_state elf_fpregset_t; #define ELF_NFPREG (sizeof(struct __riscv_d_ext_state) / sizeof(elf_fpreg_t)) +#define ELF_NVREG (sizeof(struct __riscv_v_state) / sizeof(elf_greg_t)) #if __riscv_xlen == 64 #define ELF_RISCV_R_SYM(r_info) ELF64_R_SYM(r_info) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 407464201b91..0e3c3543476c 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -26,6 +26,9 @@ enum riscv_regset { #ifdef CONFIG_FPU REGSET_F, #endif +#ifdef CONFIG_VECTOR + REGSET_V, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -92,6 +95,34 @@ static int riscv_fpr_set(struct task_struct *target, } #endif +#ifdef CONFIG_VECTOR +static int riscv_vr_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + int ret; + struct __riscv_v_state *vstate = &target->thread.vstate; + + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, vstate, 0, + offsetof(struct __riscv_v_state, vtype)); + return ret; +} + +static int riscv_vr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct __riscv_v_state *vstate = &target->thread.vstate; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0, + offsetof(struct __riscv_v_state, vtype)); + return ret; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -111,6 +142,16 @@ static const struct user_regset riscv_user_regset[] = { .set = &riscv_fpr_set, }, #endif +#ifdef CONFIG_VECTOR + [REGSET_V] = { + .core_note_type = NT_RISCV_VECTOR, + .n = ELF_NVREG, + .size = sizeof(elf_greg_t), + .align = sizeof(elf_greg_t), + .get = &riscv_vr_get, + .set = &riscv_vr_set, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 34c02e4290fe..e428f9e8710a 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -428,6 +428,7 @@ typedef struct elf64_shdr { #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */ #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ +#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */ /* Note header in a PT_NOTE section */ typedef struct elf32_note { -- 2.17.0