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[124.45.193.139]) by smtp.gmail.com with ESMTPSA id l10sm17133549pfc.125.2021.04.06.01.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 01:51:12 -0700 (PDT) Date: Tue, 6 Apr 2021 17:51:10 +0900 From: Stafford Horne To: Guo Ren Cc: Arnd Bergmann , Peter Zijlstra , linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , Guo Ren , Will Deacon , Ingo Molnar , Waiman Long , Anup Patel Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 Message-ID: <20210406085110.GD3288043@lianli.shorne-pla.net> References: <20210330223514.GE1171117@lianli.shorne-pla.net> <20210331123107.GF1171117@lianli.shorne-pla.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-csky@vger.kernel.org On Wed, Mar 31, 2021 at 11:10:53PM +0800, Guo Ren wrote: > Hi Stafford, > > How do think add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in openrisc? > > https://lore.kernel.org/linux-riscv/1617201040-83905-7-git-send-email-guoren@kernel.org/T/#u Sorry I missed your mail here. It is true that OpenRISC doesn't have xchg16, so using the xchg32 code is better. Acked-by: Stafford Horne > On Wed, Mar 31, 2021 at 8:31 PM Stafford Horne wrote: > > > > On Wed, Mar 31, 2021 at 09:23:27AM +0200, Arnd Bergmann wrote: > > > On Wed, Mar 31, 2021 at 12:35 AM Stafford Horne wrote: > > > > > > > > I just want to chime in here, there may be a better spot in the thread to > > > > mention this but, for OpenRISC I did implement some generic 8/16-bit xchg code > > > > which I have on my todo list somwhere to replace the other generic > > > > implementations like that in mips. > > > > > > > > arch/openrisc/include/asm/cmpxchg.h > > > > > > > > The idea would be that architectures just implement these methods: > > > > > > > > long cmpxchg_u32(*ptr,old,new) > > > > long xchg_u32(*ptr,val) > > > > > > > > Then the rest of the generic header would implement cmpxchg. > > > > > > I like the idea of generalizing it a little further. I'd suggest staying a > > > little closer to the existing naming here though, as we already have > > > cmpxchg() for the type-agnostic version, and cmpxchg64() for the > > > fixed-length 64-bit version. > > > > OK. > > > > > I think a nice interface between architecture-specific and architecture > > > independent code would be to have architectures provide > > > arch_cmpxchg32()/arch_xchg32() as the most basic version, as well > > > as arch_cmpxchg8()/arch_cmpxchg16()/arch_xchg8()/arch_xchg16() > > > if they have instructions for those. > > > > Thanks for the name suggestions, it makes it easier for me. > > > > > The common code can then build cmpxchg16()/xchg16() on top of > > > either the 16-bit or the 32-bit primitives, and build the cmpxchg()/xchg() > > > wrapper around those (or alternatively we can decide to have them > > > only deal with fixed-32-bit and long/pointer sized atomics). > > > > Yeah, that was the idea. > > > > -Stafford > > > > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/