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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id k9sm7332755pjo.19.2020.02.27.11.49.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Feb 2020 11:49:03 -0800 (PST) Subject: Re: [PATCH v4 3/5] target/riscv: add vector index load and store instructions To: LIU Zhiwei , alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, linux-csky@vger.kernel.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20200225103508.7651-1-zhiwei_liu@c-sky.com> <20200225103508.7651-4-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: <30ac8dcd-a6d4-b4d6-212c-6819f914bd21@linaro.org> Date: Thu, 27 Feb 2020 11:49:01 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200225103508.7651-4-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-csky-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-csky@vger.kernel.org On 2/25/20 2:35 AM, LIU Zhiwei wrote: > +vsxb_v ... 011 . ..... ..... 000 ..... 0100111 @r_nfvm > +vsxh_v ... 011 . ..... ..... 101 ..... 0100111 @r_nfvm > +vsxw_v ... 011 . ..... ..... 110 ..... 0100111 @r_nfvm > +vsxe_v ... 011 . ..... ..... 111 ..... 0100111 @r_nfvm > +vsuxb_v ... 111 . ..... ..... 000 ..... 0100111 @r_nfvm > +vsuxh_v ... 111 . ..... ..... 101 ..... 0100111 @r_nfvm > +vsuxw_v ... 111 . ..... ..... 110 ..... 0100111 @r_nfvm > +vsuxe_v ... 111 . ..... ..... 111 ..... 0100111 @r_nfvm These can be merged, with a comment, like # Vector ordered-indexed and unordered-indexed store insns. vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm which means you don't need these: > +static bool trans_vsuxb_v(DisasContext *s, arg_rnfvm* a) > +{ > + return trans_vsxb_v(s, a); > +} > + > +static bool trans_vsuxh_v(DisasContext *s, arg_rnfvm* a) > +{ > + return trans_vsxh_v(s, a); > +} > + > +static bool trans_vsuxw_v(DisasContext *s, arg_rnfvm* a) > +{ > + return trans_vsxw_v(s, a); > +} > + > +static bool trans_vsuxe_v(DisasContext *s, arg_rnfvm* a) > +{ > + return trans_vsxe_v(s, a); > +} > +static inline void vext_ld_index(void *vd, void *v0, target_ulong base, > + void *vs2, CPURISCVState *env, uint32_t desc, > + vext_get_index_addr get_index_addr, > + vext_ld_elem_fn ld_elem, > + vext_ld_clear_elem clear_elem, > + uint32_t esz, uint32_t msz, uintptr_t ra) Similar comment about merging vext_ld_index and vext_st_index. r~