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From: Guo Ren <guoren@kernel.org>
To: Greentime Hu <greentime.hu@sifive.com>,
	Dave Martin <Dave.Martin@arm.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Anup Patel <Anup.Patel@wdc.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-arch <linux-arch@vger.kernel.org>,
	Arnd Bergmann <arnd@arndb.de>,
	linux-csky@vger.kernel.org,
	linux-riscv <linux-riscv@lists.infradead.org>,
	Guo Ren <guoren@linux.alibaba.com>,
	Liu Zhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [RFC PATCH V3 00/11] riscv: Add vector ISA support
Date: Tue, 24 Mar 2020 11:41:50 +0800
Message-ID: <CAJF2gTRspXLhj1-_y6Rye7sbk2hZDEFf_AM3jcAc-=qKPru=VA@mail.gmail.com> (raw)
In-Reply-To: <CAHCEehKrzv0TozP7x9Vaq1t+Utpvqfgt=wo7eXXp0HRUKFO=WQ@mail.gmail.com>

Hi Greentime,

On Mon, Mar 23, 2020 at 12:00 PM Greentime Hu <greentime.hu@sifive.com> wrote:
>
> <guoren@kernel.org> 於 2020年3月8日 週日 下午5:50寫道:
> >
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> > 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
> >
> > The patch implement basic context switch, sigcontext save/restore and
> > ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> > is implemented. We need to discuss about vlen-size for libc sigcontext and
> > ptrace (the maximum size of vlen is unlimited in spec).
> >
> > Puzzle:
> > Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> > before, and riscv also met vlen size problem. Let's discuss the common issue
> > for all architectures and we need a better solution for unlimited vlen.
> >
> > Any help are welcomed :)
> >
> >  1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> >  2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html
> >
>
> Hi Ren,
>
> Thanks for the patch. I have some ideas about the vlen and sigcontext.
> Since vlen may not be fixed of each RISC-V cores and it could be super
> big, it means we have to allocate the memory dynamically.
> In kernel space, we may use a pointer in the context data structure.
> Something like https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/fpsimd.c#L498
> In user space, we need to let user space know the length of vector
> registers. We may create a special header in sigcontext. Something
> like https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L36
> https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L127

As you've mentioned codes above, arm64 use a fixed pre-allocate
sigcontext with a large space:

struct sigcontext {
        __u64 fault_address;
        /* AArch64 registers */
        __u64 regs[31];
        __u64 sp;
        __u64 pc;
        __u64 pstate;
        /* 4K reserved for FP/SIMD state and future expansion */
        __u8 __reserved[4096] __attribute__((__aligned__(16)));
};

There are several contexts in the space above: fpsimd, esr, sve, extra
__reserved[4096]:
 *      0x210           fpsimd_context
 *       0x10           esr_context
 *      0x8a0           sve_context (vl <= 64) (optional)
 *       0x20           extra_context (optional)
 *       0x10           terminator (null _aarch64_ctx)
 *      0x510           (reserved for future allocation)

0x210 + 0x10 + 0x8a0 + 0x20 + 0x10 + 0x510 = 4096

The max vl is 64 in arm sve, but for riscv want an unlimited size
solution and more extensible/flexible solution, such as dynamic
allocating user-space context with hwinfo. But there is no ref
solution around all arches.

There is a choice puzzle for me:
1) A pre-allocated&limited reserved size of sigcontext, the solution
has been practiced and we just need to determine the size.
2) Dynamically allocated/unlimited size of sigcontext, but may deal
with glibc, libgcc infrastructure on abi view.

Before the next stage of work, we need to choose the direction and
it's also a common puzzle for all architectures with extending
vector/simd like co-processor solutions.

ps:
Have a look on Dave's patch, he just follow the arm64 fixed
pre-allocate limited sigcontext infrastructure:
(I don't think it's a proper example for riscv vector design.)

commit d0b8cd3187889476144bd9b13bf36a932c3e7952
Author: Dave Martin <Dave.Martin@arm.com>
Date:   Tue Oct 31 15:51:03 2017 +0000

arm64/sve: Signal frame and context structure definition

>
> For the implementation in makecontext, swapcontext, getcontext,
> setcontext of glibc, we may not need to port because it seems to be
> deprecated?
> https://stackoverflow.com/questions/4298986/is-there-something-to-replace-the-ucontext-h-functions
Agree, we needn't deal with them at beginning.

>
> For the unwinding implementation of libgcc since it needs to know the
> meaning of data structure is  changed. It also need to be port.
Yes, it'll break the abi and such as the elf with -fexception compiled
will be broken.

-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

      reply index

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-08  9:49 guoren
2020-03-08  9:49 ` [RFC PATCH V3 01/11] riscv: Separate patch for cflags and aflags guoren
2020-03-08  9:49 ` [RFC PATCH V3 02/11] riscv: Rename __switch_to_aux -> fpu guoren
2020-03-08  9:49 ` [RFC PATCH V3 03/11] riscv: Extending cpufeature.c to detect V-extension guoren
2020-03-08  9:49 ` [RFC PATCH V3 04/11] riscv: Add CSR defines related to VECTOR extension guoren
2020-03-08  9:49 ` [RFC PATCH V3 05/11] riscv: Add vector feature to compile guoren
2020-03-08  9:49 ` [RFC PATCH V3 06/11] riscv: Add has_vector detect guoren
2020-03-08  9:49 ` [RFC PATCH V3 07/11] riscv: Reset vector register guoren
2020-03-08  9:49 ` [RFC PATCH V3 08/11] riscv: Add vector struct and assembler definitions guoren
2020-03-08  9:49 ` [RFC PATCH V3 09/11] riscv: Add task switch support for VECTOR guoren
2020-03-08  9:49 ` [RFC PATCH V3 10/11] riscv: Add ptrace support guoren
2020-03-08  9:49 ` [RFC PATCH V3 11/11] riscv: Add sigcontext save/restore guoren
2020-03-09  3:41 ` [RFC PATCH V3 00/11] riscv: Add vector ISA support Greentime Hu
2020-03-09 10:27   ` LIU Zhiwei
2020-03-10  8:54     ` Greentime Hu
2020-03-10  9:19       ` Greentime Hu
2020-03-12  3:14         ` LIU Zhiwei
2020-03-23  4:00 ` Greentime Hu
2020-03-24  3:41   ` Guo Ren [this message]

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