From: Paul Walmsley <paul.walmsley@sifive.com>
To: Mao Han <han_mao@c-sky.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-csky@vger.kernel.org, Greentime Hu <green.hu@gmail.com>,
Palmer Dabbelt <palmer@sifive.com>,
Christoph Hellwig <hch@lst.de>, Guo Ren <guoren@kernel.org>
Subject: Re: [PATCH V7 1/2] riscv: Add support for perf registers sampling
Date: Thu, 5 Sep 2019 00:54:08 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1909050053100.27305@viisi.sifive.com> (raw)
In-Reply-To: <49c2c29459afc59130b036eba1b1fd5155572355.1567653632.git.han_mao@c-sky.com>
On Thu, 5 Sep 2019, Mao Han wrote:
> This patch implements the perf registers sampling and validation API
> for riscv arch. The valid registers and their register ID are defined in
> perf_regs.h. Perf tool can backtrace in userspace with unwind library
> and the registers/user stack dump support.
>
> Signed-off-by: Mao Han <han_mao@c-sky.com>
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Greentime Hu <green.hu@gmail.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: linux-riscv <linux-riscv@lists.infradead.org>
> Cc: Christoph Hellwig <hch@lst.de>
> Cc: Guo Ren <guoren@kernel.org>
Thanks, queued for v5.4-rc1 with Greentime's Tested-by: (since the changes
from v6 to v7 had no functional impact).
- Paul
next prev parent reply other threads:[~2019-09-05 7:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-05 3:46 [PATCH V7 0/2] riscv: Add perf callchain support Mao Han
2019-09-05 3:46 ` [PATCH V7 1/2] riscv: Add support for perf registers sampling Mao Han
2019-09-05 7:54 ` Paul Walmsley [this message]
2019-09-05 3:46 ` [PATCH V7 2/2] riscv: Add support for libdw Mao Han
2019-09-05 7:55 ` Paul Walmsley
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