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From: Paul Walmsley <paul.walmsley@sifive.com>
To: guoren@kernel.org
Cc: palmer@dabbelt.com, aou@eecs.berkeley.edu, Anup.Patel@wdc.com,
	vincent.chen@sifive.com, zong.li@sifive.com,
	greentime.hu@sifive.com, bmeng.cn@gmail.com, atish.patra@wdc.com,
	linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	arnd@arndb.de, linux-csky@vger.kernel.org,
	linux-riscv@lists.infradead.org, Guo Ren <ren_guo@c-sky.com>
Subject: Re: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset
Date: Fri, 10 Jan 2020 17:30:45 -0800 (PST)
Message-ID: <alpine.DEB.2.21.9999.2001101730140.38813@viisi.sifive.com> (raw)
In-Reply-To: <20200105025215.2522-1-guoren@kernel.org>

On Sun, 5 Jan 2020, guoren@kernel.org wrote:

> From: Guo Ren <ren_guo@c-sky.com>
> 
> CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
> ISA Register misa. Every bit:1 indicate a feature, so we should beqz
> reset_done when there is no F/D bit in csr_msia register.
> 
> Signed-off-by: Guo Ren <ren_guo@c-sky.com>

Thanks Guo Ren, queued for v5.5-rc.


- Paul

      parent reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-05  2:52 guoren
2020-01-05  2:52 ` [PATCH 2/2] riscv: Add vector ISA support guoren
2020-01-05  8:39   ` Andreas Schwab
2020-01-05  9:01     ` Guo Ren
2020-01-05 12:32   ` kbuild test robot
2020-01-06  3:27     ` Guo Ren
2020-01-05 16:22   ` kbuild test robot
2020-01-06  2:45   ` Alan Kao
2020-01-06  3:00     ` Anup Patel
2020-01-06  3:38       ` Guo Ren
2020-01-06  3:32     ` Guo Ren
2020-01-06  9:25   ` Anup Patel
2020-01-07 16:15     ` Guo Ren
2020-01-11  1:30 ` Paul Walmsley [this message]

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