From: ira.weiny@intel.com
To: Ben Widawsky <ben.widawsky@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/4] cxl/mem: Fully decode device capability header
Date: Thu, 6 May 2021 15:36:51 -0700 [thread overview]
Message-ID: <20210506223654.1310516-2-ira.weiny@intel.com> (raw)
In-Reply-To: <20210506223654.1310516-1-ira.weiny@intel.com>
From: Ira Weiny <ira.weiny@intel.com>
Previously only the capability ID and offset were decoded.
Create a version MASK and decode the additional version and length
fields of the header.
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
drivers/cxl/core.c | 15 ++++++++++++---
drivers/cxl/cxl.h | 1 +
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
index b3c3532b53f7..21553386e218 100644
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core.c
@@ -501,12 +501,21 @@ void cxl_setup_device_regs(struct device *dev, void __iomem *base,
for (cap = 1; cap <= cap_count; cap++) {
void __iomem *register_block;
- u32 offset;
+ u32 hdr, offset, __maybe_unused length;
u16 cap_id;
+ u8 version;
+
+ hdr = readl(base + cap * 0x10);
+
+ cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK, hdr);
+ version = FIELD_GET(CXLDEV_CAP_HDR_VERSION_MASK, hdr);
+ if (version != 1)
+ dev_err(dev, "Vendor cap ID: %x incorrect version (0x%x)\n",
+ cap_id, version);
- cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
- readl(base + cap * 0x10));
offset = readl(base + cap * 0x10 + 0x4);
+ length = readl(base + cap * 0x10 + 0x8);
+
register_block = base + offset;
switch (cap_id) {
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 0211f44c95a2..9b315c069557 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -15,6 +15,7 @@
#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
/* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
+#define CXLDEV_CAP_HDR_VERSION_MASK GENMASK(23, 16)
/* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
#define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
#define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
--
2.28.0.rc0.12.gb6a658bd00c9
next prev parent reply other threads:[~2021-05-06 22:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 22:36 [PATCH 0/4] Map register blocks individually ira.weiny
2021-05-06 22:36 ` ira.weiny [this message]
2021-05-20 0:50 ` [PATCH 1/4] cxl/mem: Fully decode device capability header Dan Williams
2021-05-20 17:42 ` Ira Weiny
2021-05-06 22:36 ` [PATCH 2/4] cxl/mem: Reserve all device regions at once ira.weiny
2021-05-20 1:00 ` Dan Williams
2021-05-20 19:44 ` Ira Weiny
2021-05-06 22:36 ` [PATCH 3/4] cxl/mem: Introduce cxl_decode_register_block() ira.weiny
2021-05-06 22:36 ` [PATCH 4/4] cxl/mem: Map registers based on capabilities ira.weiny
2021-05-20 0:24 ` [PATCH 0/4] Map register blocks individually Dan Williams
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