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* [PATCH] cxl: Rename mem to pci
@ 2021-05-04 18:57 Ben Widawsky
  2021-05-10 17:29 ` Jonathan Cameron
  0 siblings, 1 reply; 6+ messages in thread
From: Ben Widawsky @ 2021-05-04 18:57 UTC (permalink / raw)
  To: linux-cxl
  Cc: Ben Widawsky, linux-pci, Alison Schofield, Dan Williams,
	Ira Weiny, Jonathan Cameron, Vishal Verma

In preparation for introducing a new driver for the CXL.mem / HDM
decoder (Host-managed Device Memory) capabilities of a CXL memory
expander, rename mem.c to pci.c so that mem.c is available for this new
driver.

CXL capabilities exist in a parallel domain to PCIe. CXL devices are
enumerable and controllable via "legacy" PCIe mechanisms; however, their
CXL capabilities are a superset of PCIe. For example, a CXL device may
be connected to a non-CXL capable PCIe root port, and therefore will not
be able to participate in CXL.mem or CXL.cache operations, but can still
be accessed through PCIe mechanisms for CXL.io operations.

To date, all existing drivers/cxl/ functionality is in support of the
PCIe-only based mechanisms, and due to the aforementioned distinction it
makes sense to move to a new file.

The result of the change is that a systems administrator may load only
the cxl_pci module and gain access to such operations as, firmware
update, offline provisioning of devices, and error collection. In
addition to freeing up the file name for another purpose, there are two
primary reasons this is useful,
    1. Acting upon devices which don't have full CXL capabilities. This
       may happen for instance if the CXL device is connected in a CXL
       unaware part of the platform topology.
    2. Userspace-first provisioning for devices without kernel driver
       interference. This may be useful when provisioning a new device
       in a specific manner that might otherwise be blocked or prevented
       by the real CXL mem driver.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 Documentation/driver-api/cxl/memory-devices.rst |  6 +++---
 drivers/cxl/Kconfig                             | 13 ++++---------
 drivers/cxl/Makefile                            |  4 ++--
 drivers/cxl/{mem.c => pci.c}                    |  9 ++++-----
 4 files changed, 13 insertions(+), 19 deletions(-)
 rename drivers/cxl/{mem.c => pci.c} (99%)

diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
index 1bad466f9167..3876ee5fea53 100644
--- a/Documentation/driver-api/cxl/memory-devices.rst
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -22,10 +22,10 @@ This section covers the driver infrastructure for a CXL memory device.
 CXL Memory Device
 -----------------
 
-.. kernel-doc:: drivers/cxl/mem.c
-   :doc: cxl mem
+.. kernel-doc:: drivers/cxl/pci.c
+   :doc: cxl pci
 
-.. kernel-doc:: drivers/cxl/mem.c
+.. kernel-doc:: drivers/cxl/pci.c
    :internal:
 
 CXL Bus
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 97dc4d751651..5483ba92b6da 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -21,15 +21,10 @@ config CXL_MEM
 	  as if the memory was attached to the typical CPU memory
 	  controller.
 
-	  Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as
-	  a module) that will attach to CXL.mem devices for
-	  configuration, provisioning, and health monitoring. This
-	  driver is required for dynamic provisioning of CXL.mem
-	  attached memory which is a prerequisite for persistent memory
-	  support. Typically volatile memory is mapped by platform
-	  firmware and included in the platform memory map, but in some
-	  cases the OS is responsible for mapping that memory. See
-	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification.
+	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
+	  configuration and management primarily via the mailbox interface. See
+	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more
+	  details.
 
 	  If unsure say 'm'.
 
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index a314a1891f4d..22a0ca59ab1b 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_CXL_BUS) += cxl_bus.o
-obj-$(CONFIG_CXL_MEM) += cxl_mem.o
+obj-$(CONFIG_CXL_MEM) += cxl_pci.o
 
 ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL
 cxl_bus-y := bus.o
-cxl_mem-y := mem.o
+cxl_pci-y := pci.o
diff --git a/drivers/cxl/mem.c b/drivers/cxl/pci.c
similarity index 99%
rename from drivers/cxl/mem.c
rename to drivers/cxl/pci.c
index 2acc6173da36..48fb3f56fc8f 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/pci.c
@@ -15,10 +15,11 @@
 #include "cxl.h"
 
 /**
- * DOC: cxl mem
+ * DOC: cxl pci
  *
- * This implements a CXL memory device ("type-3") as it is defined by the
- * Compute Express Link specification.
+ * This implements the PCI exclusive functionality for a CXL device as it is
+ * defined by the Compute Express Link specification. CXL devices may surface
+ * certain functionality even if it isn't CXL enabled.
  *
  * The driver has several responsibilities, mainly:
  *  - Create the memX device and register on the CXL bus.
@@ -26,8 +27,6 @@
  *  - Probe the device attributes to establish sysfs interface.
  *  - Provide an IOCTL interface to userspace to communicate with the device for
  *    things like firmware update.
- *  - Support management of interleave sets.
- *  - Handle and manage error conditions.
  */
 
 /*
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH] cxl: Rename mem to pci
  2021-05-04 18:57 [PATCH] cxl: Rename mem to pci Ben Widawsky
@ 2021-05-10 17:29 ` Jonathan Cameron
  2021-05-20 18:41   ` [PATCH v2] " Ben Widawsky
  0 siblings, 1 reply; 6+ messages in thread
From: Jonathan Cameron @ 2021-05-10 17:29 UTC (permalink / raw)
  To: Ben Widawsky
  Cc: linux-cxl, linux-pci, Alison Schofield, Dan Williams, Ira Weiny,
	Vishal Verma

On Tue, 4 May 2021 11:57:31 -0700
Ben Widawsky <ben.widawsky@intel.com> wrote:

> In preparation for introducing a new driver for the CXL.mem / HDM
> decoder (Host-managed Device Memory) capabilities of a CXL memory
> expander, rename mem.c to pci.c so that mem.c is available for this new
> driver.
> 
> CXL capabilities exist in a parallel domain to PCIe. CXL devices are
> enumerable and controllable via "legacy" PCIe mechanisms; however, their
> CXL capabilities are a superset of PCIe. For example, a CXL device may
> be connected to a non-CXL capable PCIe root port, and therefore will not
> be able to participate in CXL.mem or CXL.cache operations, but can still
> be accessed through PCIe mechanisms for CXL.io operations.
> 
> To date, all existing drivers/cxl/ functionality is in support of the
> PCIe-only based mechanisms, and due to the aforementioned distinction it
> makes sense to move to a new file.
> 
> The result of the change is that a systems administrator may load only
> the cxl_pci module and gain access to such operations as, firmware
> update, offline provisioning of devices, and error collection. In
> addition to freeing up the file name for another purpose, there are two
> primary reasons this is useful,
>     1. Acting upon devices which don't have full CXL capabilities. This
>        may happen for instance if the CXL device is connected in a CXL
>        unaware part of the platform topology.
>     2. Userspace-first provisioning for devices without kernel driver
>        interference. This may be useful when provisioning a new device
>        in a specific manner that might otherwise be blocked or prevented
>        by the real CXL mem driver.

The reasons here sound rather speculative to me.   Just arguing that it
makes sense from a layering point of view feels like a simpler justification,
but I'd bring this as a first patch in the series that adds the driver
that sits alongside it (as then the reasoning is self evident).

This is also going to be fun given everyone is touching the same files :)
Maybe git will cope....

Jonathan

> 
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> ---
>  Documentation/driver-api/cxl/memory-devices.rst |  6 +++---
>  drivers/cxl/Kconfig                             | 13 ++++---------
>  drivers/cxl/Makefile                            |  4 ++--
>  drivers/cxl/{mem.c => pci.c}                    |  9 ++++-----
>  4 files changed, 13 insertions(+), 19 deletions(-)
>  rename drivers/cxl/{mem.c => pci.c} (99%)
> 
> diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
> index 1bad466f9167..3876ee5fea53 100644
> --- a/Documentation/driver-api/cxl/memory-devices.rst
> +++ b/Documentation/driver-api/cxl/memory-devices.rst
> @@ -22,10 +22,10 @@ This section covers the driver infrastructure for a CXL memory device.
>  CXL Memory Device
>  -----------------
>  
> -.. kernel-doc:: drivers/cxl/mem.c
> -   :doc: cxl mem
> +.. kernel-doc:: drivers/cxl/pci.c
> +   :doc: cxl pci
>  
> -.. kernel-doc:: drivers/cxl/mem.c
> +.. kernel-doc:: drivers/cxl/pci.c
>     :internal:
>  
>  CXL Bus
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index 97dc4d751651..5483ba92b6da 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -21,15 +21,10 @@ config CXL_MEM
>  	  as if the memory was attached to the typical CPU memory
>  	  controller.
>  
> -	  Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as
> -	  a module) that will attach to CXL.mem devices for
> -	  configuration, provisioning, and health monitoring. This
> -	  driver is required for dynamic provisioning of CXL.mem
> -	  attached memory which is a prerequisite for persistent memory
> -	  support. Typically volatile memory is mapped by platform
> -	  firmware and included in the platform memory map, but in some
> -	  cases the OS is responsible for mapping that memory. See
> -	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification.
> +	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
> +	  configuration and management primarily via the mailbox interface. See
> +	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more
> +	  details.
>  
>  	  If unsure say 'm'.
>  
> diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
> index a314a1891f4d..22a0ca59ab1b 100644
> --- a/drivers/cxl/Makefile
> +++ b/drivers/cxl/Makefile
> @@ -1,7 +1,7 @@
>  # SPDX-License-Identifier: GPL-2.0
>  obj-$(CONFIG_CXL_BUS) += cxl_bus.o
> -obj-$(CONFIG_CXL_MEM) += cxl_mem.o
> +obj-$(CONFIG_CXL_MEM) += cxl_pci.o
>  
>  ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL
>  cxl_bus-y := bus.o
> -cxl_mem-y := mem.o
> +cxl_pci-y := pci.o
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/pci.c
> similarity index 99%
> rename from drivers/cxl/mem.c
> rename to drivers/cxl/pci.c
> index 2acc6173da36..48fb3f56fc8f 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/pci.c
> @@ -15,10 +15,11 @@
>  #include "cxl.h"
>  
>  /**
> - * DOC: cxl mem
> + * DOC: cxl pci
>   *
> - * This implements a CXL memory device ("type-3") as it is defined by the
> - * Compute Express Link specification.
> + * This implements the PCI exclusive functionality for a CXL device as it is
> + * defined by the Compute Express Link specification. CXL devices may surface
> + * certain functionality even if it isn't CXL enabled.
>   *
>   * The driver has several responsibilities, mainly:
>   *  - Create the memX device and register on the CXL bus.
> @@ -26,8 +27,6 @@
>   *  - Probe the device attributes to establish sysfs interface.
>   *  - Provide an IOCTL interface to userspace to communicate with the device for
>   *    things like firmware update.
> - *  - Support management of interleave sets.
> - *  - Handle and manage error conditions.
>   */
>  
>  /*


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2] cxl: Rename mem to pci
  2021-05-10 17:29 ` Jonathan Cameron
@ 2021-05-20 18:41   ` Ben Widawsky
  2021-05-20 19:39     ` Dan Williams
  0 siblings, 1 reply; 6+ messages in thread
From: Ben Widawsky @ 2021-05-20 18:41 UTC (permalink / raw)
  To: linux-cxl
  Cc: Jonathan Cameron, Alison Schofield, Dan Williams, Ira Weiny,
	Vishal Verma, Ben Widawsky

As the driver has undergone development, it's become clear that the
majority [entirety?] of the current functionality in mem.c is actually a
layer encapsulating functionality exposed through PCI based
interactions. This layer can be used either in isolation or to provide
functionality for higher level functionality.

CXL capabilities exist in a parallel domain to PCIe. CXL devices are
enumerable and controllable via "legacy" PCIe mechanisms; however, their
CXL capabilities are a superset of PCIe. For example, a CXL device may
be connected to a non-CXL capable PCIe root port, and therefore will not
be able to participate in CXL.mem or CXL.cache operations, but can still
be accessed through PCIe mechanisms for CXL.io operations.

To properly represent the PCI nature of this driver, and in preparation for
introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device
Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that
mem.c is available for this new driver.

The result of the change is that there is a clear layering distinction
in the driver, and a systems administrator may load only the cxl_pci
module and gain access to such operations as, firmware update, offline
provisioning of devices, and error collection. In addition to freeing up
the file name for another purpose, there are two primary reasons this is
useful,
    1. Acting upon devices which don't have full CXL capabilities. This
       may happen for instance if the CXL device is connected in a CXL
       unaware part of the platform topology.
    2. Userspace-first provisioning for devices without kernel driver
       interference. This may be useful when provisioning a new device
       in a specific manner that might otherwise be blocked or prevented
       by the real CXL mem driver.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
v2: Makes it clear that the main motivation for this patch is for proper
layering and that administrative PCI-only activities is a secondary benefit.

I'm proposing we take the hit now and merge this as our next patch for cxl/next.

---
 Documentation/driver-api/cxl/memory-devices.rst |  6 +++---
 drivers/cxl/Kconfig                             | 13 ++++---------
 drivers/cxl/Makefile                            |  5 +++--
 drivers/cxl/{mem.c => pci.c}                    |  9 ++++-----
 4 files changed, 14 insertions(+), 19 deletions(-)
 rename drivers/cxl/{mem.c => pci.c} (99%)

diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
index 71495ed77069..a927169db984 100644
--- a/Documentation/driver-api/cxl/memory-devices.rst
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -22,10 +22,10 @@ This section covers the driver infrastructure for a CXL memory device.
 CXL Memory Device
 -----------------
 
-.. kernel-doc:: drivers/cxl/mem.c
-   :doc: cxl mem
+.. kernel-doc:: drivers/cxl/pci.c
+   :doc: cxl pci
 
-.. kernel-doc:: drivers/cxl/mem.c
+.. kernel-doc:: drivers/cxl/pci.c
    :internal:
 
 CXL Core
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 97dc4d751651..5483ba92b6da 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -21,15 +21,10 @@ config CXL_MEM
 	  as if the memory was attached to the typical CPU memory
 	  controller.
 
-	  Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as
-	  a module) that will attach to CXL.mem devices for
-	  configuration, provisioning, and health monitoring. This
-	  driver is required for dynamic provisioning of CXL.mem
-	  attached memory which is a prerequisite for persistent memory
-	  support. Typically volatile memory is mapped by platform
-	  firmware and included in the platform memory map, but in some
-	  cases the OS is responsible for mapping that memory. See
-	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification.
+	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
+	  configuration and management primarily via the mailbox interface. See
+	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more
+	  details.
 
 	  If unsure say 'm'.
 
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index 3808e39dd31f..10b204025d3b 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -1,7 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_CXL_BUS) += cxl_core.o
-obj-$(CONFIG_CXL_MEM) += cxl_mem.o
+obj-$(CONFIG_CXL_MEM) += cxl_pci.o
 
 ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL
 cxl_core-y := core.o
-cxl_mem-y := mem.o
+cxl_pci-y := pci.o
+cxl_acpi-y := acpi.o
diff --git a/drivers/cxl/mem.c b/drivers/cxl/pci.c
similarity index 99%
rename from drivers/cxl/mem.c
rename to drivers/cxl/pci.c
index c5fdf2c57181..c7996c2a2054 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/pci.c
@@ -16,10 +16,11 @@
 #include "mem.h"
 
 /**
- * DOC: cxl mem
+ * DOC: cxl pci
  *
- * This implements a CXL memory device ("type-3") as it is defined by the
- * Compute Express Link specification.
+ * This implements the PCI exclusive functionality for a CXL device as it is
+ * defined by the Compute Express Link specification. CXL devices may surface
+ * certain functionality even if it isn't CXL enabled.
  *
  * The driver has several responsibilities, mainly:
  *  - Create the memX device and register on the CXL bus.
@@ -27,8 +28,6 @@
  *  - Probe the device attributes to establish sysfs interface.
  *  - Provide an IOCTL interface to userspace to communicate with the device for
  *    things like firmware update.
- *  - Support management of interleave sets.
- *  - Handle and manage error conditions.
  */
 
 #define cxl_doorbell_busy(cxlm)                                                \
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH v2] cxl: Rename mem to pci
  2021-05-20 18:41   ` [PATCH v2] " Ben Widawsky
@ 2021-05-20 19:39     ` Dan Williams
  2021-05-26 17:44       ` [PATCH v3] " Ben Widawsky
  0 siblings, 1 reply; 6+ messages in thread
From: Dan Williams @ 2021-05-20 19:39 UTC (permalink / raw)
  To: Ben Widawsky
  Cc: linux-cxl, Jonathan Cameron, Alison Schofield, Ira Weiny, Vishal Verma

On Thu, May 20, 2021 at 11:41 AM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> As the driver has undergone development, it's become clear that the
> majority [entirety?] of the current functionality in mem.c is actually a
> layer encapsulating functionality exposed through PCI based
> interactions. This layer can be used either in isolation or to provide
> functionality for higher level functionality.
>
> CXL capabilities exist in a parallel domain to PCIe. CXL devices are
> enumerable and controllable via "legacy" PCIe mechanisms; however, their
> CXL capabilities are a superset of PCIe. For example, a CXL device may
> be connected to a non-CXL capable PCIe root port, and therefore will not
> be able to participate in CXL.mem or CXL.cache operations, but can still
> be accessed through PCIe mechanisms for CXL.io operations.
>
> To properly represent the PCI nature of this driver, and in preparation for
> introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device
> Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that
> mem.c is available for this new driver.
>
> The result of the change is that there is a clear layering distinction
> in the driver, and a systems administrator may load only the cxl_pci
> module and gain access to such operations as, firmware update, offline
> provisioning of devices, and error collection. In addition to freeing up
> the file name for another purpose, there are two primary reasons this is
> useful,
>     1. Acting upon devices which don't have full CXL capabilities. This
>        may happen for instance if the CXL device is connected in a CXL
>        unaware part of the platform topology.
>     2. Userspace-first provisioning for devices without kernel driver
>        interference. This may be useful when provisioning a new device
>        in a specific manner that might otherwise be blocked or prevented
>        by the real CXL mem driver.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> ---
> v2: Makes it clear that the main motivation for this patch is for proper
> layering and that administrative PCI-only activities is a secondary benefit.
>
> I'm proposing we take the hit now and merge this as our next patch for cxl/next.

Looks good to me, and I think low risk to expedite into cxl/next to
remove the burden on git to cope with other development touching these
files.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v3] cxl: Rename mem to pci
  2021-05-20 19:39     ` Dan Williams
@ 2021-05-26 17:44       ` Ben Widawsky
  2021-05-26 18:01         ` Ben Widawsky
  0 siblings, 1 reply; 6+ messages in thread
From: Ben Widawsky @ 2021-05-26 17:44 UTC (permalink / raw)
  To: linux-cxl, Dan Williams
  Cc: Jonathan Cameron, Alison Schofield, Ira Weiny, Vishal Verma,
	Ben Widawsky

As the driver has undergone development, it's become clear that the
majority [entirety?] of the current functionality in mem.c is actually a
layer encapsulating functionality exposed through PCI based
interactions. This layer can be used either in isolation or to provide
functionality for higher level functionality.

CXL capabilities exist in a parallel domain to PCIe. CXL devices are
enumerable and controllable via "legacy" PCIe mechanisms; however, their
CXL capabilities are a superset of PCIe. For example, a CXL device may
be connected to a non-CXL capable PCIe root port, and therefore will not
be able to participate in CXL.mem or CXL.cache operations, but can still
be accessed through PCIe mechanisms for CXL.io operations.

To properly represent the PCI nature of this driver, and in preparation for
introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device
Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that
mem.c is available for this new driver.

The result of the change is that there is a clear layering distinction
in the driver, and a systems administrator may load only the cxl_pci
module and gain access to such operations as, firmware update, offline
provisioning of devices, and error collection. In addition to freeing up
the file name for another purpose, there are two primary reasons this is
useful,
    1. Acting upon devices which don't have full CXL capabilities. This
       may happen for instance if the CXL device is connected in a CXL
       unaware part of the platform topology.
    2. Userspace-first provisioning for devices without kernel driver
       interference. This may be useful when provisioning a new device
       in a specific manner that might otherwise be blocked or prevented
       by the real CXL mem driver.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 Documentation/driver-api/cxl/memory-devices.rst |  6 +++---
 drivers/cxl/Kconfig                             | 13 ++++---------
 drivers/cxl/Makefile                            |  4 ++--
 drivers/cxl/{mem.c => pci.c}                    |  9 ++++-----
 4 files changed, 13 insertions(+), 19 deletions(-)
 rename drivers/cxl/{mem.c => pci.c} (99%)

diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
index 71495ed77069..a927169db984 100644
--- a/Documentation/driver-api/cxl/memory-devices.rst
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -22,10 +22,10 @@ This section covers the driver infrastructure for a CXL memory device.
 CXL Memory Device
 -----------------
 
-.. kernel-doc:: drivers/cxl/mem.c
-   :doc: cxl mem
+.. kernel-doc:: drivers/cxl/pci.c
+   :doc: cxl pci
 
-.. kernel-doc:: drivers/cxl/mem.c
+.. kernel-doc:: drivers/cxl/pci.c
    :internal:
 
 CXL Core
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 97dc4d751651..5483ba92b6da 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -21,15 +21,10 @@ config CXL_MEM
 	  as if the memory was attached to the typical CPU memory
 	  controller.
 
-	  Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as
-	  a module) that will attach to CXL.mem devices for
-	  configuration, provisioning, and health monitoring. This
-	  driver is required for dynamic provisioning of CXL.mem
-	  attached memory which is a prerequisite for persistent memory
-	  support. Typically volatile memory is mapped by platform
-	  firmware and included in the platform memory map, but in some
-	  cases the OS is responsible for mapping that memory. See
-	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification.
+	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
+	  configuration and management primarily via the mailbox interface. See
+	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more
+	  details.
 
 	  If unsure say 'm'.
 
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index 3808e39dd31f..d9d282dc15be 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_CXL_BUS) += cxl_core.o
-obj-$(CONFIG_CXL_MEM) += cxl_mem.o
+obj-$(CONFIG_CXL_MEM) += cxl_pci.o
 
 ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL
 cxl_core-y := core.o
-cxl_mem-y := mem.o
+cxl_pci-y := pci.o
diff --git a/drivers/cxl/mem.c b/drivers/cxl/pci.c
similarity index 99%
rename from drivers/cxl/mem.c
rename to drivers/cxl/pci.c
index c5fdf2c57181..c7996c2a2054 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/pci.c
@@ -16,10 +16,11 @@
 #include "mem.h"
 
 /**
- * DOC: cxl mem
+ * DOC: cxl pci
  *
- * This implements a CXL memory device ("type-3") as it is defined by the
- * Compute Express Link specification.
+ * This implements the PCI exclusive functionality for a CXL device as it is
+ * defined by the Compute Express Link specification. CXL devices may surface
+ * certain functionality even if it isn't CXL enabled.
  *
  * The driver has several responsibilities, mainly:
  *  - Create the memX device and register on the CXL bus.
@@ -27,8 +28,6 @@
  *  - Probe the device attributes to establish sysfs interface.
  *  - Provide an IOCTL interface to userspace to communicate with the device for
  *    things like firmware update.
- *  - Support management of interleave sets.
- *  - Handle and manage error conditions.
  */
 
 #define cxl_doorbell_busy(cxlm)                                                \
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH v3] cxl: Rename mem to pci
  2021-05-26 17:44       ` [PATCH v3] " Ben Widawsky
@ 2021-05-26 18:01         ` Ben Widawsky
  0 siblings, 0 replies; 6+ messages in thread
From: Ben Widawsky @ 2021-05-26 18:01 UTC (permalink / raw)
  To: linux-cxl, Dan Williams
  Cc: Jonathan Cameron, Alison Schofield, Ira Weiny, Vishal Verma

On 21-05-26 10:44:13, Ben Widawsky wrote:
> As the driver has undergone development, it's become clear that the
> majority [entirety?] of the current functionality in mem.c is actually a
> layer encapsulating functionality exposed through PCI based
> interactions. This layer can be used either in isolation or to provide
> functionality for higher level functionality.
> 
> CXL capabilities exist in a parallel domain to PCIe. CXL devices are
> enumerable and controllable via "legacy" PCIe mechanisms; however, their
> CXL capabilities are a superset of PCIe. For example, a CXL device may
> be connected to a non-CXL capable PCIe root port, and therefore will not
> be able to participate in CXL.mem or CXL.cache operations, but can still
> be accessed through PCIe mechanisms for CXL.io operations.
> 
> To properly represent the PCI nature of this driver, and in preparation for
> introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device
> Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that
> mem.c is available for this new driver.
> 
> The result of the change is that there is a clear layering distinction
> in the driver, and a systems administrator may load only the cxl_pci
> module and gain access to such operations as, firmware update, offline
> provisioning of devices, and error collection. In addition to freeing up
> the file name for another purpose, there are two primary reasons this is
> useful,
>     1. Acting upon devices which don't have full CXL capabilities. This
>        may happen for instance if the CXL device is connected in a CXL
>        unaware part of the platform topology.
>     2. Userspace-first provisioning for devices without kernel driver
>        interference. This may be useful when provisioning a new device
>        in a specific manner that might otherwise be blocked or prevented
>        by the real CXL mem driver.
> 
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>

[snip]

I forgot to put the reasoning for v3...

I accidentally left acpi.o in the Makefile. The only diff from v2 is acpi.o is
dropped.

Ben

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-05-26 18:01 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-04 18:57 [PATCH] cxl: Rename mem to pci Ben Widawsky
2021-05-10 17:29 ` Jonathan Cameron
2021-05-20 18:41   ` [PATCH v2] " Ben Widawsky
2021-05-20 19:39     ` Dan Williams
2021-05-26 17:44       ` [PATCH v3] " Ben Widawsky
2021-05-26 18:01         ` Ben Widawsky

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