linux-cxl.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH] cxl/pci: Rename CXL REGLOC ID
@ 2021-06-18  0:30 Ben Widawsky
  2021-06-18  0:33 ` Dan Williams
  0 siblings, 1 reply; 3+ messages in thread
From: Ben Widawsky @ 2021-06-18  0:30 UTC (permalink / raw)
  To: linux-cxl; +Cc: Ben Widawsky, Dan Williams

The current naming is confusing and wrong. The Register Locator is
identified by the DSVSEC identifier, not an offset.

Cc: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 drivers/cxl/pci.c | 2 +-
 drivers/cxl/pci.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index f8408e5f0754..4cf351a3cf99 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -1086,7 +1086,7 @@ static int cxl_mem_setup_regs(struct cxl_mem *cxlm)
 	LIST_HEAD(register_maps);
 	int ret = 0;
 
-	regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_OFFSET);
+	regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID);
 	if (!regloc) {
 		dev_err(dev, "register location dvsec not found\n");
 		return -ENXIO;
diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
index af3ec078cf6c..dad7a831f65f 100644
--- a/drivers/cxl/pci.h
+++ b/drivers/cxl/pci.h
@@ -13,7 +13,7 @@
 #define PCI_DVSEC_VENDOR_ID_CXL		0x1E98
 #define PCI_DVSEC_ID_CXL		0x0
 
-#define PCI_DVSEC_ID_CXL_REGLOC_OFFSET		0x8
+#define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID	0x8
 #define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET	0xC
 
 /* BAR Indicator Register (BIR) */
-- 
2.32.0


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] cxl/pci: Rename CXL REGLOC ID
  2021-06-18  0:30 [PATCH] cxl/pci: Rename CXL REGLOC ID Ben Widawsky
@ 2021-06-18  0:33 ` Dan Williams
  2021-06-18 13:37   ` Jonathan Cameron
  0 siblings, 1 reply; 3+ messages in thread
From: Dan Williams @ 2021-06-18  0:33 UTC (permalink / raw)
  To: Ben Widawsky; +Cc: linux-cxl

On Thu, Jun 17, 2021 at 5:30 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> The current naming is confusing and wrong. The Register Locator is
> identified by the DSVSEC identifier, not an offset.
>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>

LGTM.

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] cxl/pci: Rename CXL REGLOC ID
  2021-06-18  0:33 ` Dan Williams
@ 2021-06-18 13:37   ` Jonathan Cameron
  0 siblings, 0 replies; 3+ messages in thread
From: Jonathan Cameron @ 2021-06-18 13:37 UTC (permalink / raw)
  To: Dan Williams; +Cc: Ben Widawsky, linux-cxl

On Thu, 17 Jun 2021 17:33:52 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> On Thu, Jun 17, 2021 at 5:30 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
> >
> > The current naming is confusing and wrong. The Register Locator is
> > identified by the DSVSEC identifier, not an offset.
> >
> > Cc: Dan Williams <dan.j.williams@intel.com>
> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>  
> 
> LGTM.
Likewise. oops ;)

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2021-06-18 13:38 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-18  0:30 [PATCH] cxl/pci: Rename CXL REGLOC ID Ben Widawsky
2021-06-18  0:33 ` Dan Williams
2021-06-18 13:37   ` Jonathan Cameron

This is a public inbox, see mirroring instructions
on how to clone and mirror all data and code used for this inbox