From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Ben Widawsky" <ben.widawsky@intel.com>,
<linux-cxl@vger.kernel.org>
Subject: Re: [PATCH V2 3/3] cxl/mem: Adjust ram/pmem range to represent DPA ranges
Date: Fri, 18 Jun 2021 15:03:51 +0100 [thread overview]
Message-ID: <20210618150351.00004ccc@Huawei.com> (raw)
In-Reply-To: <20210617221620.1904031-4-ira.weiny@intel.com>
On Thu, 17 Jun 2021 15:16:20 -0700
<ira.weiny@intel.com> wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> CXL spec defines the volatile DPA range to be 0 to Volatile memory size.
> It further defines the persistent DPA range to follow directly after the
> end of the Volatile DPA through the persistent memory size.
Reference would be good for anyone sanity checking against the spec. I think it's
Table 176 that says this.
> Essentially
>
> Volatile DPA range = [0, Volatile size)
> Persistent DPA range = [Volatile size, Volatile size + Persistent size)
>
> Adjust the pmem_range start to reflect this and remote the TODO.
remove
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/pci.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 341885345b53..a1fd7923dfb9 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -1635,8 +1635,9 @@ static int cxl_mem_create_range_info(struct cxl_mem *cxlm)
> if (cxlm->partition_align_bytes == 0) {
> cxlm->ram_range.start = 0;
> cxlm->ram_range.end = cxlm->volatile_only_bytes - 1;
> - cxlm->pmem_range.start = 0;
> - cxlm->pmem_range.end = cxlm->persistent_only_bytes - 1;
> + cxlm->pmem_range.start = cxlm->volatile_only_bytes;
> + cxlm->pmem_range.end = cxlm->volatile_only_bytes +
> + cxlm->persistent_only_bytes - 1;
> return 0;
> }
>
> @@ -1660,15 +1661,12 @@ static int cxl_mem_create_range_info(struct cxl_mem *cxlm)
> cxlm->next_volatile_bytes,
> cxlm->next_persistent_bytes);
>
> - /*
> - * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias.
> - * For now, only the capacity is exported in sysfs
> - */
> cxlm->ram_range.start = 0;
> cxlm->ram_range.end = cxlm->active_volatile_bytes - 1;
>
> - cxlm->pmem_range.start = 0;
> - cxlm->pmem_range.end = cxlm->active_persistent_bytes - 1;
> + cxlm->pmem_range.start = cxlm->active_volatile_bytes;
> + cxlm->pmem_range.end = cxlm->active_volatile_bytes +
> + cxlm->active_persistent_bytes - 1;
>
> return 0;
> }
next prev parent reply other threads:[~2021-06-18 14:04 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 22:16 [PATCH V2 0/3] Query and use Partition Info ira.weiny
2021-06-17 22:16 ` [PATCH V2 1/3] cxl/pci: Store memory capacity values ira.weiny
2021-06-18 13:40 ` Jonathan Cameron
2021-06-17 22:16 ` [PATCH V2 2/3] cxl/mem: Account for partitionable space in ram/pmem ranges ira.weiny
2021-06-18 13:59 ` Jonathan Cameron
2021-06-18 16:30 ` Ira Weiny
2021-06-18 16:31 ` [PATCH V3] " ira.weiny
2021-06-18 16:58 ` Ben Widawsky
2021-06-18 18:48 ` Ira Weiny
2021-06-18 19:32 ` Ben Widawsky
2021-08-11 1:49 ` [PATCH v4 2/3] " Dan Williams
2021-06-17 22:16 ` [PATCH V2 3/3] cxl/mem: Adjust ram/pmem range to represent DPA ranges ira.weiny
2021-06-18 14:03 ` Jonathan Cameron [this message]
2021-06-21 19:54 ` [PATCH V3] " ira.weiny
2021-10-27 22:40 ` [PATCH 0/9] CDAT/DSMAS reading and cleanups ira.weiny
2021-10-27 22:40 ` [PATCH 1/9] Documentation/auxiliary_bus: Clarify auxiliary_device creation ira.weiny
2021-10-27 22:40 ` [PATCH 2/9] Documentation/auxiliary_bus: Clarify match_name ira.weiny
2021-10-27 22:40 ` [PATCH 3/9] Documentation/auxiliary_bus: Update Auxiliary device lifespan ira.weiny
2021-10-27 22:43 ` [PATCH 0/9] CDAT/DSMAS reading and cleanups Ira Weiny
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