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From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, Ira Weiny <ira.weiny@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 0/3] Rework register enumeration for later reuse
Date: Fri, 16 Jul 2021 16:15:45 -0700	[thread overview]
Message-ID: <20210716231548.174778-1-ben.widawsky@intel.com> (raw)

In order to plug a cxl_memdev into cxl_core for the purpose of enumerating HDM
decoders, the physical address of the component registers must be known and
retained at the time of cxl_memdev creation. The cxl_mem driver already
enumerates and maps these registers. The main goal of the series is to be able
to reuse that logic for the upcoming cxl_memdev driver.

This patch series is based upon the core-reorg patches I submitted yesterday,
but it could be merged independently. With core-reorg [1] series, and the
expand-decoders [2] patch, everything is in place to implement the region and
memdev drivers.

A few other options were discussed/pursued:
1. Passing around the mapped addresses instead of physical. This caused more
   churn in the existing code. It also causes a somewhat undesirable combination
   of having one entity "own" the mapping and another one using it.
2. Don't map component registers in cxl_pci, and instead map it when needed in
   the port driver. I actually believe this would have been the right thing to
   do except certain register sets (like IDE) may be needed by the cxl_pci
   driver anyway.
3. Export functionality to obtain component register mapping in cxl_core and let
   the cxl_pci driver and memdev driver use that. This solution might be the
   eventual solution, but it's not yet necessary.
3b. Copy the enumeration code from pci.c into the new memdev driver.
4. Obtaining the register mapping from cxl_mem at driver probe since the
   cxl_memdev and cxl_mem are connected. Like #1, this mixes "ownership" of the
   mapping.

[1]: https://lore.kernel.org/linux-cxl/20210715194125.898305-1-ben.widawsky@intel.com/
[2]: https://lore.kernel.org/linux-cxl/20210706160050.527553-1-ben.widawsky@intel.com/

Ben Widawsky (3):
  cxl/pci: Ignore unknown register block types
  cxl/pci: Simplify register setup
  cxl/pci: Retain map information in cxl_mem_probe

 drivers/cxl/cxl.h |  1 -
 drivers/cxl/pci.c | 50 ++++++++++++++++++++---------------------------
 drivers/cxl/pci.h |  1 +
 3 files changed, 22 insertions(+), 30 deletions(-)


-- 
2.32.0


             reply	other threads:[~2021-07-16 23:16 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-16 23:15 Ben Widawsky [this message]
2021-07-16 23:15 ` [PATCH 1/3] cxl/pci: Ignore unknown register block types Ben Widawsky
2021-08-02 15:49   ` Jonathan Cameron
2021-07-16 23:15 ` [PATCH 2/3] cxl/pci: Simplify register setup Ben Widawsky
2021-08-02 15:50   ` Jonathan Cameron
2021-07-16 23:15 ` [PATCH 3/3] cxl/pci: Retain map information in cxl_mem_probe Ben Widawsky
2021-08-02 15:56   ` Jonathan Cameron
2021-08-02 16:10     ` Dan Williams
2021-08-02 17:09       ` Dan Williams
2021-08-03  7:58         ` Jonathan Cameron

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