linux-cxl.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 11/23] cxl: Enable an endpoint decoder type
Date: Fri, 23 Jul 2021 14:06:11 -0700	[thread overview]
Message-ID: <20210723210623.114073-12-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210723210623.114073-1-ben.widawsky@intel.com>

Endpoints have decoders too (no dports)

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 drivers/cxl/acpi.c     | 14 +++++------
 drivers/cxl/core/bus.c | 55 ++++++++++++++++++++++++++++++++++++++----
 drivers/cxl/cxl.h      | 28 +++++++++++++--------
 3 files changed, 75 insertions(+), 22 deletions(-)

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index fee56688d797..fd1ae2495ab0 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -108,13 +108,13 @@ static void cxl_add_cfmws_decoders(struct device *dev)
 		}
 
 		flags = cfmws_to_decoder_flags(cfmws->restrictions);
-		cxld = devm_cxl_add_decoder(dev, NULL,
-					    CFMWS_INTERLEAVE_WAYS(cfmws),
-					    cfmws->base_hpa, cfmws->window_size,
-					    CFMWS_INTERLEAVE_WAYS(cfmws),
-					    CFMWS_INTERLEAVE_GRANULARITY(cfmws),
-					    CXL_DECODER_EXPANDER,
-					    flags);
+		cxld = devm_cxl_add_platform_decoder(dev,
+						     CFMWS_INTERLEAVE_WAYS(cfmws),
+						     cfmws->base_hpa,
+						     cfmws->window_size,
+						     CFMWS_INTERLEAVE_WAYS(cfmws),
+						     CFMWS_INTERLEAVE_GRANULARITY(cfmws),
+						     flags);
 
 		if (IS_ERR(cxld)) {
 			dev_err(dev, "Failed to add decoder for %#llx-%#llx\n",
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
index 7c75ae7f3b8e..e2166f43aefc 100644
--- a/drivers/cxl/core/bus.c
+++ b/drivers/cxl/core/bus.c
@@ -84,6 +84,8 @@ static ssize_t target_type_show(struct device *dev,
 	struct cxl_decoder *cxld = to_cxl_decoder(dev);
 
 	switch (cxld->target_type) {
+	case CXL_DECODER_UNKNOWN:
+		return sysfs_emit(buf, "unknown\n");
 	case CXL_DECODER_ACCELERATOR:
 		return sysfs_emit(buf, "accelerator\n");
 	case CXL_DECODER_EXPANDER:
@@ -176,6 +178,12 @@ static const struct attribute_group *cxl_decoder_switch_attribute_groups[] = {
 	NULL,
 };
 
+static const struct attribute_group *cxl_decoder_endpoint_attribute_groups[] = {
+	&cxl_decoder_base_attribute_group,
+	&cxl_base_attribute_group,
+	NULL,
+};
+
 static void cxl_decoder_release(struct device *dev)
 {
 	struct cxl_decoder *cxld = to_cxl_decoder(dev);
@@ -189,6 +197,12 @@ static void cxl_decoder_release(struct device *dev)
 	kfree(cxld);
 }
 
+static const struct device_type cxl_decoder_endpoint_type = {
+	.name = "cxl_decoder_endpoint",
+	.release = cxl_decoder_release,
+	.groups = cxl_decoder_endpoint_attribute_groups,
+};
+
 static const struct device_type cxl_decoder_switch_type = {
 	.name = "cxl_decoder_switch",
 	.release = cxl_decoder_release,
@@ -516,10 +530,12 @@ cxl_decoder_alloc(struct cxl_port *port, int nr_targets, resource_size_t base,
 	dev->bus = &cxl_bus_type;
 
 	/* platform decoders don't have a parent */
-	if (port)
-		dev->type = &cxl_decoder_switch_type;
-	else
+	if (!port)
 		dev->type = &cxl_decoder_root_type;
+	else if (flags & CXL_DECODER_F_ENDPOINT)
+		dev->type = &cxl_decoder_endpoint_type;
+	else
+		dev->type = &cxl_decoder_switch_type;
 
 	return cxld;
 err:
@@ -527,7 +543,7 @@ cxl_decoder_alloc(struct cxl_port *port, int nr_targets, resource_size_t base,
 	return ERR_PTR(rc);
 }
 
-struct cxl_decoder *
+static struct cxl_decoder *
 devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
 		     resource_size_t base, resource_size_t len,
 		     int interleave_ways, int interleave_granularity,
@@ -560,7 +576,36 @@ devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
 	put_device(dev);
 	return ERR_PTR(rc);
 }
-EXPORT_SYMBOL_GPL(devm_cxl_add_decoder);
+
+struct cxl_decoder *
+devm_cxl_add_platform_decoder(struct device *host, int nr_targets,
+			      resource_size_t base, resource_size_t len,
+			      int interleave_ways, int interleave_granularity,
+			      unsigned long flags)
+{
+	return devm_cxl_add_decoder(host, NULL, nr_targets, base, len,
+				    interleave_ways, interleave_granularity, 0,
+				    flags);
+}
+EXPORT_SYMBOL_GPL(devm_cxl_add_platform_decoder);
+
+struct cxl_decoder *devm_cxl_add_switch_decoder(struct device *host,
+						struct cxl_port *port,
+						enum cxl_decoder_type type)
+{
+	return devm_cxl_add_decoder(host, port, 0, 0, 0, 0, 0,
+				    CXL_DECODER_UNKNOWN, 0);
+}
+EXPORT_SYMBOL_GPL(devm_cxl_add_switch_decoder);
+
+struct cxl_decoder *devm_cxl_add_endpoint_decoder(struct device *host,
+						  struct cxl_port *port,
+						  enum cxl_decoder_type type)
+{
+	return devm_cxl_add_decoder(host, port, 0, 0, 0, 0, 0, type,
+				    CXL_DECODER_F_ENDPOINT);
+}
+EXPORT_SYMBOL_GPL(devm_cxl_add_endpoint_decoder);
 
 /**
  * __cxl_driver_register - register a driver for the cxl bus
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b9302d3861f0..dcf2d1a59271 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -173,11 +173,13 @@ int cxl_map_device_regs(struct pci_dev *pdev,
 #define CXL_DECODER_F_TYPE2 BIT(2)
 #define CXL_DECODER_F_TYPE3 BIT(3)
 #define CXL_DECODER_F_LOCK  BIT(4)
-#define CXL_DECODER_F_MASK  GENMASK(4, 0)
+#define CXL_DECODER_F_ENDPOINT BIT(5)
+#define CXL_DECODER_F_MASK GENMASK(5, 0)
 
 enum cxl_decoder_type {
-       CXL_DECODER_ACCELERATOR = 2,
-       CXL_DECODER_EXPANDER = 3,
+	CXL_DECODER_UNKNOWN = 0,
+	CXL_DECODER_ACCELERATOR = 2,
+	CXL_DECODER_EXPANDER = 3,
 };
 
 /**
@@ -271,12 +273,19 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,
 
 struct cxl_decoder *to_cxl_decoder(struct device *dev);
 bool is_root_decoder(struct device *dev);
-struct cxl_decoder *
-devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
-		     resource_size_t base, resource_size_t len,
-		     int interleave_ways, int interleave_granularity,
-		     enum cxl_decoder_type type, unsigned long flags);
 
+struct cxl_decoder *
+devm_cxl_add_platform_decoder(struct device *host, int nr_targets,
+			      resource_size_t base, resource_size_t len,
+			      int interleave_ways, int interleave_granularity,
+			      unsigned long flags);
+
+struct cxl_decoder *devm_cxl_add_switch_decoder(struct device *host,
+						struct cxl_port *port,
+						enum cxl_decoder_type type);
+struct cxl_decoder *devm_cxl_add_endpoint_decoder(struct device *host,
+						  struct cxl_port *port,
+						  enum cxl_decoder_type type);
 /*
  * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
  * single ported host-bridges need not publish a decoder capability when a
@@ -287,8 +296,7 @@ devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
 static inline struct cxl_decoder *
 devm_cxl_add_passthrough_decoder(struct device *host)
 {
-	return devm_cxl_add_decoder(host, NULL, 1, 0, 0, 1, PAGE_SIZE,
-				    CXL_DECODER_EXPANDER, 0);
+	return devm_cxl_add_platform_decoder(host, 1, 0, 0, 1, PAGE_SIZE, 0);
 }
 
 extern struct bus_type cxl_bus_type;
-- 
2.32.0


  parent reply	other threads:[~2021-07-23 21:06 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-23 21:06 [PATCH RFCish 00/23] cxl_region and cxl_memdev drivers Ben Widawsky
2021-07-23 21:06 ` [PATCH 01/23] cxl: Move cxl_core to new directory Ben Widawsky
2021-07-23 21:06 ` [PATCH 02/23] cxl/core: Improve CXL core kernel docs Ben Widawsky
2021-07-23 21:06 ` [PATCH 03/23] cxl/core: Extract register and pmem functionality Ben Widawsky
2021-07-23 21:06 ` [PATCH 04/23] cxl/mem: Move character device region creation Ben Widawsky
2021-07-23 21:06 ` [PATCH 05/23] cxl: Pass fops and shutdown to memdev creation Ben Widawsky
2021-07-23 21:06 ` [PATCH 06/23] cxl/core: Move memdev management to core Ben Widawsky
2021-07-23 21:06 ` [PATCH 07/23] cxl/pci: Ignore unknown register block types Ben Widawsky
2021-07-23 21:06 ` [PATCH 08/23] cxl/pci: Simplify register setup Ben Widawsky
2021-07-23 21:06 ` [PATCH 09/23] cxl/pci: Retain map information in cxl_mem_probe Ben Widawsky
2021-07-23 21:06 ` [PATCH 10/23] cxl/decoder: Support parentless decoders Ben Widawsky
2021-07-30 21:03   ` Dan Williams
2021-07-23 21:06 ` Ben Widawsky [this message]
2021-07-23 21:06 ` [PATCH 12/23] cxl/region: Add region creation ABI Ben Widawsky
2021-08-14  2:19   ` Dan Williams
2021-08-26 21:01     ` Ben Widawsky
2021-08-26 21:44       ` Dan Williams
2021-07-23 21:06 ` [PATCH 13/23] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-07-23 21:06 ` [PATCH 14/23] cxl: Convert driver id to an enum Ben Widawsky
2021-07-23 21:06 ` [PATCH 15/23] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-07-23 21:06 ` [PATCH 16/23] cxl/core: Convert decoder range to resource Ben Widawsky
2021-07-23 21:06 ` [PATCH 17/23] cxl/region: Handle region's address space allocation Ben Widawsky
2021-07-23 21:06 ` [PATCH 18/23] cxl/region: Only allow CXL capable targets Ben Widawsky
2021-07-23 21:06 ` [PATCH 19/23] cxl/mem: Introduce CXL mem driver Ben Widawsky
2021-07-23 21:06 ` [PATCH 20/23] cxl/memdev: Determine CXL.mem capability Ben Widawsky
2021-07-23 21:06 ` [PATCH 21/23] cxl/mem: Check that the device is CXL.mem capable Ben Widawsky
2021-07-23 21:06 ` [PATCH 22/23] cxl/mem: Add device as a port Ben Widawsky
2021-07-23 21:06 ` [PATCH 23/23] cxl/core: Map component registers for ports Ben Widawsky

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210723210623.114073-12-ben.widawsky@intel.com \
    --to=ben.widawsky@intel.com \
    --cc=Jonathan.Cameron@Huawei.com \
    --cc=alison.schofield@intel.com \
    --cc=dan.j.williams@intel.com \
    --cc=ira.weiny@intel.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=vishal.l.verma@intel.com \
    --subject='Re: [PATCH 11/23] cxl: Enable an endpoint decoder type' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).