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From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 19/23] cxl/mem: Introduce CXL mem driver
Date: Fri, 23 Jul 2021 14:06:19 -0700	[thread overview]
Message-ID: <20210723210623.114073-20-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210723210623.114073-1-ben.widawsky@intel.com>

CXL endpoints that participate in the CXL.mem protocol require extra
control to ensure architectural constraints are met for device
management.

This driver will implement those controls.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 drivers/cxl/Makefile      |  3 ++-
 drivers/cxl/core/bus.c    |  2 ++
 drivers/cxl/core/memdev.c |  5 +++++
 drivers/cxl/cxl.h         |  1 +
 drivers/cxl/mem.c         | 45 +++++++++++++++++++++++++++++++++++++++
 drivers/cxl/mem.h         |  2 ++
 6 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 drivers/cxl/mem.c

diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index 5b8ada0b7c3b..e5e210369502 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -1,10 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_CXL_BUS) += core/
-obj-$(CONFIG_CXL_MEM) += cxl_pci.o cxl_region.o
+obj-$(CONFIG_CXL_MEM) += cxl_mem.o cxl_pci.o cxl_region.o
 obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
 obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
 
 cxl_acpi-y := acpi.o
+cxl_mem-y := mem.o
 cxl_pci-y := pci.o
 cxl_acpi-y := acpi.o
 cxl_pmem-y := pmem.o
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
index baf4d4308ae5..ecaa0bcb7fe4 100644
--- a/drivers/cxl/core/bus.c
+++ b/drivers/cxl/core/bus.c
@@ -740,6 +740,8 @@ static int cxl_device_id(struct device *dev)
 		return CXL_DEVICE_NVDIMM;
 	if (is_cxl_region(dev))
 		return CXL_DEVICE_REGION;
+	if (is_cxl_memdev(dev))
+		return CXL_DEVICE_ENDPOINT;
 	return 0;
 }
 
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index bdf811c02b4d..45894164560b 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -217,3 +217,8 @@ devm_cxl_add_memdev(struct device *host, struct cxl_mem *cxlm,
 	return ERR_PTR(rc);
 }
 EXPORT_SYMBOL_GPL(devm_cxl_add_memdev);
+
+bool is_cxl_memdev(struct device *dev)
+{
+	return dev->type == &cxl_memdev_type;
+}
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 9975b4ecf78b..640006ba457f 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -321,6 +321,7 @@ enum cxl_driver_id {
 	CXL_DEVICE_NVDIMM_BRIDGE,
 	CXL_DEVICE_NVDIMM,
 	CXL_DEVICE_REGION,
+	CXL_DEVICE_ENDPOINT,
 };
 
 struct cxl_driver {
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
new file mode 100644
index 000000000000..2997a03abcb6
--- /dev/null
+++ b/drivers/cxl/mem.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
+#include <linux/device.h>
+#include <linux/module.h>
+#include "mem.h"
+
+/**
+ * DOC: cxl mem
+ *
+ * CXL memory endpoint devices are CXL capable devices that are participating in
+ * CXL.mem protocol. Their functionality builds on top of the CXL.io protocol
+ * that allows enumerating and configuring a CXL endpoint via standard PCI
+ * mechanisms.
+ */
+
+static int cxl_memdev_probe(struct device *dev)
+{
+	return -EOPNOTSUPP;
+}
+
+static void cxl_memdev_remove(struct device *dev)
+{
+}
+
+static struct cxl_driver cxl_memdev_driver = {
+	.name = "cxl_memdev",
+	.probe = cxl_memdev_probe,
+	.remove = cxl_memdev_remove,
+	.id = CXL_DEVICE_ENDPOINT,
+};
+
+static __init int cxl_memdev_init(void)
+{
+	return cxl_driver_register(&cxl_memdev_driver);
+}
+
+static __exit void cxl_memdev_exit(void)
+{
+	cxl_driver_unregister(&cxl_memdev_driver);
+}
+
+MODULE_LICENSE("GPL v2");
+module_init(cxl_memdev_init);
+module_exit(cxl_memdev_exit);
+MODULE_IMPORT_NS(CXL);
diff --git a/drivers/cxl/mem.h b/drivers/cxl/mem.h
index 27e142cb0c55..d5c0cd541277 100644
--- a/drivers/cxl/mem.h
+++ b/drivers/cxl/mem.h
@@ -98,4 +98,6 @@ static inline bool is_cxl_mem_capable(struct cxl_memdev *cxlmd)
 	return false;
 }
 
+bool is_cxl_memdev(struct device *dev);
+
 #endif /* __CXL_MEM_H__ */
-- 
2.32.0


  parent reply	other threads:[~2021-07-23 21:06 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-23 21:06 [PATCH RFCish 00/23] cxl_region and cxl_memdev drivers Ben Widawsky
2021-07-23 21:06 ` [PATCH 01/23] cxl: Move cxl_core to new directory Ben Widawsky
2021-07-23 21:06 ` [PATCH 02/23] cxl/core: Improve CXL core kernel docs Ben Widawsky
2021-07-23 21:06 ` [PATCH 03/23] cxl/core: Extract register and pmem functionality Ben Widawsky
2021-07-23 21:06 ` [PATCH 04/23] cxl/mem: Move character device region creation Ben Widawsky
2021-07-23 21:06 ` [PATCH 05/23] cxl: Pass fops and shutdown to memdev creation Ben Widawsky
2021-07-23 21:06 ` [PATCH 06/23] cxl/core: Move memdev management to core Ben Widawsky
2021-07-23 21:06 ` [PATCH 07/23] cxl/pci: Ignore unknown register block types Ben Widawsky
2021-07-23 21:06 ` [PATCH 08/23] cxl/pci: Simplify register setup Ben Widawsky
2021-07-23 21:06 ` [PATCH 09/23] cxl/pci: Retain map information in cxl_mem_probe Ben Widawsky
2021-07-23 21:06 ` [PATCH 10/23] cxl/decoder: Support parentless decoders Ben Widawsky
2021-07-30 21:03   ` Dan Williams
2021-07-23 21:06 ` [PATCH 11/23] cxl: Enable an endpoint decoder type Ben Widawsky
2021-07-23 21:06 ` [PATCH 12/23] cxl/region: Add region creation ABI Ben Widawsky
2021-08-14  2:19   ` Dan Williams
2021-08-26 21:01     ` Ben Widawsky
2021-08-26 21:44       ` Dan Williams
2021-07-23 21:06 ` [PATCH 13/23] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-07-23 21:06 ` [PATCH 14/23] cxl: Convert driver id to an enum Ben Widawsky
2021-07-23 21:06 ` [PATCH 15/23] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-07-23 21:06 ` [PATCH 16/23] cxl/core: Convert decoder range to resource Ben Widawsky
2021-07-23 21:06 ` [PATCH 17/23] cxl/region: Handle region's address space allocation Ben Widawsky
2021-07-23 21:06 ` [PATCH 18/23] cxl/region: Only allow CXL capable targets Ben Widawsky
2021-07-23 21:06 ` Ben Widawsky [this message]
2021-07-23 21:06 ` [PATCH 20/23] cxl/memdev: Determine CXL.mem capability Ben Widawsky
2021-07-23 21:06 ` [PATCH 21/23] cxl/mem: Check that the device is CXL.mem capable Ben Widawsky
2021-07-23 21:06 ` [PATCH 22/23] cxl/mem: Add device as a port Ben Widawsky
2021-07-23 21:06 ` [PATCH 23/23] cxl/core: Map component registers for ports Ben Widawsky

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