From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCADAC43219 for ; Tue, 21 Sep 2021 22:05:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA6B360FA0 for ; Tue, 21 Sep 2021 22:05:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235895AbhIUWGf (ORCPT ); Tue, 21 Sep 2021 18:06:35 -0400 Received: from mga14.intel.com ([192.55.52.115]:40124 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235889AbhIUWGf (ORCPT ); Tue, 21 Sep 2021 18:06:35 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10114"; a="223119121" X-IronPort-AV: E=Sophos;i="5.85,311,1624345200"; d="scan'208";a="223119121" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 15:05:05 -0700 X-IronPort-AV: E=Sophos;i="5.85,311,1624345200"; d="scan'208";a="557114665" Received: from ksankar-mobl2.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.132.1]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 15:05:04 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Cc: Ben Widawsky , Alison Schofield , Dan Williams , Ira Weiny , Jonathan Cameron , Vishal Verma Subject: [PATCH 2/7] cxl/pci: Remove dev_dbg for unknown register blocks Date: Tue, 21 Sep 2021 15:04:54 -0700 Message-Id: <20210921220459.2437386-3-ben.widawsky@intel.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210921220459.2437386-1-ben.widawsky@intel.com> References: <20210921220459.2437386-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org While interesting to driver developers, the dev_dbg message doesn't do much except clutter up logs. This information should be attainable through sysfs, and someday lspci like utilities. This change additionally helps reduce the LOC in a subsequent patch to refactor some of cxl_pci register mapping. Signed-off-by: Ben Widawsky --- drivers/cxl/pci.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 64180f46c895..ccc7c2573ddc 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -475,9 +475,6 @@ static int cxl_pci_setup_regs(struct cxl_mem *cxlm) cxl_decode_register_block(reg_lo, reg_hi, &bar, &offset, ®_type); - dev_dbg(dev, "Found register block in bar %u @ 0x%llx of type %u\n", - bar, offset, reg_type); - /* Ignore unknown register block types */ if (reg_type > CXL_REGLOC_RBI_MEMDEV) continue; -- 2.33.0