From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Cc: Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 0/7] cxl_pci refactor for reusability
Date: Tue, 21 Sep 2021 15:14:57 -0700 [thread overview]
Message-ID: <20210921221457.brtvzrgdkokc5nie@intel.com> (raw)
In-Reply-To: <20210921220459.2437386-1-ben.widawsky@intel.com>
On 21-09-21 15:04:52, Ben Widawsky wrote:
> Provide the ability to obtain CXL register blocks as discrete functionality.
> This functionality will become useful for other CXL drivers that need access to
> CXL register blocks. It is also in line with other additions to core which moves
> register mapping functionality.
>
> At the introduction of the CXL driver the only user of CXL MMIO was cxl_pci
> (then known as cxl_mem). As the driver has evolved it is clear that cxl_pci will
> not be the only entity that needs access to CXL MMIO. This series stops short of
> moving the generalized functionality into cxl_core for the sake of getting eyes
> on the important foundational bits sooner rather than later. The ultimate plan
> is to move much of the code into cxl_core.
>
> Via review of two previous patches [1] & [2] it has been suggested that the bits
> which are being used for DVSEC enumeration move into PCI core. As CXL core is
> soon going to require these, let's try to get the ball rolling now on making
> that happen.
>
> [1]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/
Dangit.
https://lore.kernel.org/linux-pci/20210913190131.xiiszmno46qie7v5@intel.com/
> [2]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/
>
> Ben Widawsky (7):
> cxl: Convert "RBI" to enum
> cxl/pci: Remove dev_dbg for unknown register blocks
> cxl/pci: Refactor cxl_pci_setup_regs
> cxl/pci: Make more use of cxl_register_map
> PCI: Add pci_find_dvsec_capability to find designated VSEC
> cxl/pci: Use pci core's DVSEC functionality
> ocxl: Use pci core's DVSEC functionality
>
> drivers/cxl/pci.c | 144 ++++++++++++++++++-------------------
> drivers/cxl/pci.h | 14 ++--
> drivers/misc/ocxl/config.c | 13 +---
> drivers/pci/pci.c | 32 +++++++++
> include/linux/pci.h | 1 +
> 5 files changed, 113 insertions(+), 91 deletions(-)
>
> --
> 2.33.0
>
next prev parent reply other threads:[~2021-09-21 22:15 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 22:04 [PATCH 0/7] cxl_pci refactor for reusability Ben Widawsky
2021-09-21 22:04 ` [PATCH 1/7] cxl: Convert "RBI" to enum Ben Widawsky
2021-09-21 22:04 ` [PATCH 2/7] cxl/pci: Remove dev_dbg for unknown register blocks Ben Widawsky
2021-09-21 22:04 ` [PATCH 3/7] cxl/pci: Refactor cxl_pci_setup_regs Ben Widawsky
2021-09-21 23:39 ` Dan Williams
2021-09-22 4:31 ` Ben Widawsky
2021-09-21 22:04 ` [PATCH 4/7] cxl/pci: Make more use of cxl_register_map Ben Widawsky
2021-09-21 22:04 ` [PATCH 5/7] PCI: Add pci_find_dvsec_capability to find designated VSEC Ben Widawsky
2021-09-22 9:33 ` Frederic Barrat
2021-09-21 22:04 ` [PATCH 6/7] cxl/pci: Use pci core's DVSEC functionality Ben Widawsky
2021-09-21 22:04 ` [PATCH 7/7] ocxl: " Ben Widawsky
2021-09-22 0:44 ` Dan Williams
2021-09-22 9:38 ` Frederic Barrat
2021-09-21 22:14 ` Ben Widawsky [this message]
2021-09-21 22:28 ` [PATCH 0/7] cxl_pci refactor for reusability Dan Williams
2021-09-21 23:03 ` Ben Widawsky
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